Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization
ID
683174
Date
5/28/2025
Public
1.3.2.1. Using Simulation Signal Activity Data in Power Analysis
1.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation
1.3.2.3. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities
1.3.2.4. Signal Activities from User Defaults Only
1.5.1. Complete Design Simulation Power Analysis Flow
1.5.2. Modular Design Simulation Power Analysis Flow
1.5.3. Multiple Simulation Power Analysis Flow
1.5.4. Overlapping Simulation Power Analysis Flow
1.5.5. Partial Design Simulation Power Analysis Flow
1.5.6. Vectorless Estimation Power Analysis Flow
2.4.1. Clock Power Management
2.4.2. Pipelining and Retiming
2.4.3. Architectural Optimization
2.4.4. I/O Power Guidelines
2.4.5. Dynamically Controlled On-Chip Terminations (OCT)
2.4.6. Memory Optimization (M20K/MLAB)
2.4.7. DDR Memory Controller Settings
2.4.8. DSP Implementation
2.4.9. Reducing High-Speed Tile (HST) Usage
2.4.10. Unused Transceiver Channels
2.4.11. Periphery Power reduction XCVR Settings
2.3.1. Power-Driven Synthesis
Synthesis netlist optimization occurs during the synthesis stage of the compilation flow. You can apply these settings on a project or entity level.
The Power Optimization During Synthesis logic option determines how aggressively Analysis & Synthesis optimizes the design for power. To access this option at a project level, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis).
Settings | Description | Optimization Techniques Included |
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Off | The Compiler does not perform netlist, placement, or routing optimizations to minimize power. | - |
Normal compilation (Default) | The Compiler applies low compute effort algorithms to minimize power through netlist optimizations that do not reduce design performance. |
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Extra effort | Besides the techniques in the Normal compilation setting, the Compiler applies high-compute-effort algorithms to minimize power through netlist optimizations. Selecting this option might impact performance. |
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You can also control memory optimization options from the Quartus® Prime Settings dialog box. The Default Parameters page allows you to edit the Low_Power_Mode parameter. The settings for this parameter are equivalent to the values of the Power Optimization During Synthesis logic options. The Low_Power_Mode parameter always takes precedence over the Optimize Power for Synthesis option for power optimization on memory.
Parameter Value | Equivalent Setting in Power Optimization During Synthesis Logic Option |
---|---|
None | Off |
Auto | Normal compilation |
All | Extra effort |