Stratix V Hard IP for PCI Express IP Core Release Notes

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ID 683165
Date 10/31/2016
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1. Stratix V Hard IP for PCI Express IP Core Release Notes
1. Stratix V Hard IP for PCI Express IP Core Release Notes x
1.1. Stratix V Hard IP for PCI Express IP Core v16.1 1.2. Stratix V Hard IP for PCI Express IP Core v16.0 1.3. Stratix V Hard IP for PCI Express IP Core v15.0 1.4. Stratix V Hard IP for PCI Express IP Core v14.1 1.5. Stratix V Hard IP for PCI Express IP Core v14.0 1.6. Stratix V Hard IP for PCI Express IP Core v13.1
1. Stratix V Hard IP for PCI Express IP Core Release Notes

1.5. Stratix V Hard IP for PCI Express IP Core v14.0

Table 5.  v14.0 June 2014
Description Impact
Added preliminary support for Stratix V Hard IP for PCI Express with SR-IOV (Single Root I/O Virtualization). -
Made the following changes for the V-Series PCIe with Avalon-MM DMA Interface (previously called the Avalon-MM 256-bit Hard IP for PCI Express IP Core).
  • Revised programming model and optimized the performance of the Descriptor Controller.
  • Added support for either 128- or 256-bit interface to the Application Layer.
  • Added support for 64-bit addressing, making address translation unnecessary.
  • Added support for optional bursting RX Master for BAR2.
  • Added access to selected Configuration Space registers and link status registers through the optional Control Register Access (CRA) Avalon-MM slave port.
  • Added parameters to enable 256 completion tags with completion tag checking performed in Application Layer.
  • Simulation support for Phase 2 and Phase 3 equalization when requested by third-party BFM for Gen3 variants.
  • Due to the many changes, the support level has reverted to preliminary.
The Descriptor Controller IP core included in the 14.0 release is significantly different from the one included in 13.1. Altera recommends that you update to v14.0. Altera no longer support v13.1.
Made the following changes to the Avalon-MM Stratix V Hard IP for PCI Express IP core:
  • Added access to selected Configuration Space registers and link status registers through the optional Control Register Access (CRA) Avalon-MM slave port.
  • Added optional hard IP status bus that includes signals necessary to connect the Transceiver Reconfiguration Controller IP Core.
  • Added optional hard IP status extension bus which includes signals that are useful for debugging, including: link training, status, error, and Configuration Space signals.
  • Added support for 64-bit addressing, making address translation unnecessary.
  • Added parameters to enable 256 completion tags with completion tag checking performed in Application Layer.
  • Simulation support for Phase 2 and Phase 3 equalization when requested by third-party BFM.
  • Increased CRA address to 14 bits from 12 bits.
All of these new features are optional. If you include an optional feature that changes the port signature of your IP core, you must regenerate your design and connect the signals
Upgraded the Avalon-ST version to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores. -
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