Stratix V Hard IP for PCI Express IP Core Release Notes

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ID 683165
Date 10/31/2016
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1. Stratix V Hard IP for PCI Express IP Core Release Notes
1. Stratix V Hard IP for PCI Express IP Core Release Notes x
1.1. Stratix V Hard IP for PCI Express IP Core v16.1 1.2. Stratix V Hard IP for PCI Express IP Core v16.0 1.3. Stratix V Hard IP for PCI Express IP Core v15.0 1.4. Stratix V Hard IP for PCI Express IP Core v14.1 1.5. Stratix V Hard IP for PCI Express IP Core v14.0 1.6. Stratix V Hard IP for PCI Express IP Core v13.1
1. Stratix V Hard IP for PCI Express IP Core Release Notes

1.3. Stratix V Hard IP for PCI Express IP Core v15.0

Table 3.  v15.0 May 2015
Description Impact
In IP core variations with the Avalon-MM DMA interface, added support for downstream burst read request for a payload of size up to 4 KBytes, if Enable burst capability for RXM BAR2 port is turned on in the Parameter Editor. Previous maximum downstream read request payload size was 512 bytes. If you choose the Avalon-MM DMA interface, the IP core can receive and process a burst read request for a payload of any size supported by the PCI Express specification (up to 4 KBytes), if it receives such a burst read request on the PCI Express link.
In IP core variations with the Avalon-MM interface, added support to send message TLPs with data payload of any length from a Root Port. If you choose the Avalon-MM interface, a Root Port IP core can send messages with payload greater than 1 dword.
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