Tandem Motion-Power 48 V Board Reference Manual

ID 683164
Date 11/05/2020
Public

Tandem Motion-Power 48 V Board Functional Description

Figure 2. Block Diagram

Power Connectors

The DC inputs are a 6-pin Molex (up to 200W), 4-pin DIN (up to 100W) or 6-pin pluggable terminal block to suit a range of standard power supplies. The board offers directly wired connection to other power supplies or batteries and a direct connection to the DC link, bypassing the DC-DC boost converter.

HSMC Connector

Signals connecting the Tandem Motion board to the development kit are buffered and level shifted for compatibility with a number of development kits. A configurable I/O power supply allows interfacing with common I/O standards implemented on Intel FPGAs.

MAX 10 ADC Connector

Analog signals are available on a 20-pin header for connection to a suitable development kit that includes ADCs. The pinout matches that of J20 on the Intel® MAX® 10 10M50 development kit.

DC-DC Boost Converter

The DC-DC boost converter hardware consists of two phases that both provide bidirectional power flow from a low voltage power source or battery (typically 12 V DC) to a DC bus (typically 48 V DC) that feeds the motor drive inverters. The DC-DC provides the boost function to increase the voltage of the DC link. It also provides a buck function during periods of regenerative braking to deliver power from the DC bus back to the low voltage source (i.e. battery in this case). Enable regeneration by pulling down pin 3 of the battery connector, J1. If you do not attach an energy storage element to the DC bus, disable regeneration.

The DC input voltage, DC link voltage, DC link current and the currents in each DC-DC phase are sensed and converted to digital signals which must be used to implement a control loop for the DC-DC boost function in the FPGA on the attached development kit. Intel reference designs targeting the Tandem Motion board contain a controller developed using DSP Builder for Intel FPGAs Advanced Blockset for Simulink, which enables model-based design, automatic HDL code generation and automatic ModelSim testbench generation.

Power Supplies

A switch-mode buck-boost converter provides a 24 V supply, which drives a number of downstream regulators. This arrangement enables the board to operate with variable DC link voltages or with power input through the DC-DC bypass connector.

Multiple Enpirion ER3125 devices provide 12 V, 5 V and 3.3 V supplies to logic and other circuits on the board.

The board provides a configurable I/O voltage for the connections to the development kit. You configure I/O voltage by populating one or more zero-ohm resistors.

Drive Inverters

The board has six N-channel MOSFET half bridges, nominally arranged as two three-phase inverters for driving three-phase motors. You can use the half bridges in other arrangements, e.g. to drive stepper motors.

Encoder Interfaces

The encoder interfaces apply the appropriate voltage translation and buffering for each encoder type.

Quadrature and Hall sensor encoders use three differential pairs to connect to the board.

EnDAT and BiSS encoders are connected via an RS-485 serial bus.

A Tamagawa AU6805 Resolver-Digital Converter (RDC) provides the resolver interface for each drive axis. The AU6805 supports 12- and 16-bit absolute position over a serial interface together with quadrature equivalent and Hall sensor equivalent feedback signals in parallel.

Analog Signal Conditioning and Conversion

In addition to the analog connector for MAX10 ADCs, the board also includes sigma-delta modulators to support digital connections to FPGAs that do not have integrated ADCs. You must implement a suitable demodulator in the FPGA, as described in Intel application note AN 773 and datasheet DS-1038.

The board implements current sensing with low Ohmic value shunt resistors. The board connects the resulting sense voltage directly to the sigma-delta modulator or through a sense amplifier to the MAX10 ADC input.

You can add a low-pass filter to the inputs to the sigma-delta ADCs but in all cases the demodulator IP in the FPGA filters them.

For the direct MAX10 inputs, sense amplifiers scale and offset the inputs to allow bipolar signals (e.g., bidirectional current flow) to be sampled with the MAX 10 ADC that can only convert signals between 0 V and its reference voltage. Remove the offset during processing of the samples in software. The sense amplifier circuit has a low-pass filter, scaled by five times and offset by 1.25 V.

The input current and DC bus current are only available via sigma-delta ADCs. Both sense circuits employ analog anti-aliasing circuitry with cut-off frequencies around 7 kHz before the sigma-delta ADC, for consistency with other DC-DC converter signals that are sampled at 16 kHz.

The board implements voltage sensing with voltage dividers connected directly to the sigma-delta or MAX 10 ADC inputs, with low pass filtering.

The input current and DC bus current are not available as analog signals to the MAX 10 ADCs, so do not have filter cut-off frequencies. The board samples motor phase currents at the quiet points of the PWM waveforms (refer to Intel applicaztion notes AN669, AN773, and datasheet DS-1038). The filtering inherent in the sigma-delta demodulation is sufficient, so the board uses no additional analog anti-aliasing filters.

Table 1.  Analog Low Pass FilteringShows details of cut-off frequencies for analog anti-aliasing filters.
Signal Anti-aliasing cut-off frequency forAnti-aliasing cut-off frequency for
Sigma-delta ADCs (kHz) MAX 10 ADCs (kHz)
Motor phase voltages 0.73 754
DC bus voltage 7.3 6.2
Input voltage 7.4 6.8
Input current 7.7 N/A
Boost inductor current 7.7 6.8
DC bus current 7.7 N/A
Motor phase currents N/A 14

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