Embedded Peripherals IP User Guide

ID 683130
Date 9/18/2024
Public
Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. HPS GMII to RGMII Adapter Intel® FPGA IP 51. Intel FPGA MII to RMII Converter Core 52. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 53. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 54. Intel FPGA MSI to GIC Generator Core 55. Cache Coherency Translator Intel® FPGA IP 56. Lightweight UART Core

52.5. Interface

Figure 176. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Intel® FPGA IP Top Level Interfaces
Table 489.  Top Level I/O Port List
Signal Width Direction Description

Interface Name: peri_clock

Description: Peripheral clock interface

clk 1 Input Peripheral clock source

Interface Name: peri_reset

Description: Peripheral reset interface

rst_n 1 Input

Active low peripheral asynchronous reset source.

This signal is asynchronously asserted and synchronously de-asserted. The synchronous de-assertion must be provided external to this core.

Interface Name: avalon_slave

Description: Avalon® MM agent interface for CSR access of this core

addr 1 Input Avalon® memory-mapped interface address bus. The address bus is in the unit of word addressing.
read 1 Input Avalon® memory-mapped interface read control
write 1 Input Avalon® memory-mapped interface write control
writedata 32 Input Avalon® memory-mapped interface write data bus
readdata 32 Output Avalon® memory-mapped interface read data bus

Interface name: hps_gmii

Description: Conduit interface connected to HPS EMAC GMII/MII interface

mac_tx_clk_o 1 Input GMII/MII transmit clock from HPS
mac_tx_clk_i 1 Output GMII/MII transmit clock to HPS
mac_rx_clk 1 Output GMII/MII receive clock to HPS
mac_rst_tx_n 1 Input GMII/MII transmit reset source from HPS. Active low reset.
mac_rst_rx_n 1 Input GMII/MII receive reset source from HPS. Active low reset.
mac_txd 8 Input GMII/MII transmit data from HPS
mac_txen 1 Input GMII/MII transmit enable from HPS
mac_txer 1 Input GMII/MII transmit error from HPS
mac_rxdv 1 Output GMII/MII receive data valid to HPS
mac_rxer 1 Output GMII/MII receive data error to HPS
mac_rxd 8 Output GMII/MII receive data to HPS
mac_col 1 Output GMII/MII collision detect to HPS
mac_crs 1 Output GMII/MII carrier sense to HPS
mac_speed 2 Input MAC speed indication from HPS

Interface name: pcs_transmit_reset

Description: Transmit reset source from HPS

pcs_rst_tx 1 Output Inverted version of mac_rst_tx_n. Active high reset.

Interface name: pcs_receive_reset

Description: Receive reset source from HPS

pcs_rst_rx 1 Output Inverted version of mac_rst_rx_n. Active high reset.

Interface name: pcs_transmit_clock

Description: Transmit clock from PCS block

pcs_tx_clk 1 Input Transmit clock from PCS block.

Interface name: pcs_receive_clock

Description: Receive clock from PCS block

pcs_rx_clk 1 Input Receive clock from PCS block

Interface name: pcs_clock_enable

Description: Transmit and receive clock enabler from PCS block

pcs_txclk_ena 1 Input Transmit clock enabler from PCS block. This signal enables the pcs_tx_clk.
pcs_rxclk_ena 1 Input Receive clock enabler from PCS block. This signal enables the pcs_rx_clk.

Interface name: pcs_gmii

Description: GMII interface to the PCS block

pcs_gmii_rx_dv 1 Input Receive data valid from PCS block
pcs_gmii_rx_d 8 Input Receive data from PCS block
pcs_gmii_rx_err 1 Input Receive data error from PCS block
pcs_gmii_tx_en 1 Output Transmit data enable to PCS block
pcs_gmii_tx_d 8 Output Transmit data to PCS block
pcs_gmii_tx_err 1 Output Transmit data error to PCS block

Interface name: pcs_mii

Description: MII interface to the PCS block

pcs_mii_rx_dv 1 Input Receive data valid from PCS block
pcs_mii_rx_d 4 Input Receive data from PCS block
pcs_mii_rx_err 1 Input Receive data error from PCS block
pcs_mii_tx_en 1 Output Transmit data enable to PCS block
pcs_mii_tx_d 4 Output Transmit data to PCS block
pcs_mii_tx_err 1 Output Transmit data error to PCS block
pcs_mii_col 1 Input Collision detect from PCS block
pcs_mii_crs 1 Input Carrier sense from PCS block