Embedded Peripherals IP User Guide

ID 683130
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP

20.4. Driver API

Table 201.  alt_epcq_controller2_lock
Prototype: alt_epcq_controller2_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock)
Include: <altera_epcq_controller2.h>
Parameter:
  • flash_info – pointer to general flash device structure
  • sector_to_lock- block protection bits in EPCQ
Return: Return 0 if successful and otherwise return:
  • -EINVAL for Invalid argument
  • -ETIME for Time out and skipping the looping after 0.7sec
  • -ENOLCK for Sectors lock failed
Description: Lock the range of memory sector which protected from write and erase.
Table 202.  alt_epcq_controller2_get_info
Prototype: alt_epcq_controller2_get_info(alt_flash_dev *fd, flash_region **info, int *number_of_regions)
Include: <altera_epcq_controller2.h>
Parameter:
  • fd – pointer to general flash device structure
  • info- pointer to the flash region
  • number_of_regions- pointer to the number of regions
Return: Return 0 if successful and otherwise return:
  • -EINVAL for Invalid argument
  • -EIO for possibly hardware problem
Description: Pass the table of erase blocks to the user. The flash returns a single flash region that gives the number and size of sectors for the device used.
Table 203.  alt_epcq_controller2_erase_block
Prototype: alt_epcq_controller2_erase_block(alt_flash_dev *flash_info, int block_offset)
Include: <altera_epcq_controller2.h>
Parameter:
  • flash_info – pointer to general flash device structure
  • block_offset- byte-addressed offset, from start of flash of the sector to be erased
Return: Return 0 if successful and otherwise return:
  • -EINVAL for Invalid argument
  • -EIO for erase failed and sector might be protected
Description: Erase a single flash sector.
Table 204.  alt_epcq_controller2_write_block
Prototype: alt_epcq_controller2_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length)
Include: <altera_epcq_controller2.h>
Parameter:
  • flash_info – pointer to general flash device structure
  • block_offset- byte-addressed offset, from start of flash of the sector to be written
  • data-offset – byte offset (unaligned access) of write into memory
  • data – data to be written
  • length – size of writing
Return: Return 0 if successful and otherwise return:
  • -EINVAL for Invalid argument
  • -EIO for write failed and sector might be protected
Description: Write one block/sector of data to the flash. The length of the write cannot spill into the adjacent sector.
Table 205.  alt_epcq_controller2_write
Prototype: alt_epcq_controller2_write (alt_flash_dev *flash_info, int offset, const void *src_addr, int length)
Include: <altera_epcq_controller2.h>
Parameter:
  • flash_info – pointer to general flash device structure
  • offset- byte offset (unaligned access) of write to flash memory
  • src_addr – source buffer
  • length – size of writing
Return: Return 0 if successful and otherwise return:
  • -EINVAL for Invalid argument
  • -EIO for write failed and sector might be protected
Description: Program the data into the flash at the selected address. This function automatically erases a block as needed.
Table 206.  alt_epcq_controller2_read
Prototype: alt_epcq_controller2_read(alt_flash_dev *flash_info, int offset, void* dest_addr, int length)
Include: <altera_epcq_controller2.h>
Parameter:
  • flash_info – pointer to general flash device structure
  • offset- byte offset read from flash memory
  • dest_addr – destination buffer
  • length – size of writing
Return: Return 0 if successful and otherwise return:
  • -EINVAL for Invalid argument
Description: Read data from flash at the selected address.