JESD204C Intel® FPGA IP User Guide

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ID 683108
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel FPGA IP User Guide 2. Overview of the JESD204C Intel FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the JESD204C Intel® FPGA IP 6. JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the JESD204C Intel® FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. JESD204C Intel® FPGA IP Features 2.4. Presets 2.5. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the JESD204C Intel® FPGA IP x
5.1. JESD204C TX and RX Reset Sequence 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the JESD204C Intel FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the JESD204C Intel® FPGA IP
6. JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the JESD204C Intel® FPGA IP User Guide

8.1. Transmitter Registers

Table 27.  lane_ctrl_commonCommon lane control and assignment. The common lane control applies to all lanes in the link.

Offset: 0x0

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:2 Reserved Reserved RV 0x0
1 scr_disable Setting this bit disables TX scrambler RW Compile-time specific
0 bit_reversal

This is a compile-time option that you need to set before IP generation.

0 = LSB-first serialization.

1 = MSB-first serialization.

Note: The JESD204C converter device may support either MSB-first serialization or LSB-first serialization.

When bit_reversal = 1, the word aligner reverses TX parallel data bits before transmitting it to the PMA for serialization. For example; in 64-bit mode => D[63:0] is rewired to D[0:63]

RO Compile-time specific
Table 28.  lane_ctrl_0Lane control and assignment for Lane 0.

Offset: 0x4
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 29.  lane_ctrl_1Lane control and assignment for Lane 1.

Offset: 0x8
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 30.  lane_ctrl_2Lane control and assignment for Lane 2.

Offset: 0xC
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 31.  lane_ctrl_3Lane control and assignment for Lane 3.

Offset: 0x10
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 32.  lane_ctrl_4Lane control and assignment for Lane 4.

Offset: 0x14
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 33.  lane_ctrl_5Lane control and assignment for Lane 5.

Offset: 0x18
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 34.  lane_ctrl_6Lane control and assignment for Lane 6.

Offset: 0x1C
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 35.  lane_ctrl_7Lane control and assignment for Lane 7.

Offset: 0x20
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 36.  lane_ctrl_8Lane control and assignment for Lane 8.

Offset: 0x24
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 37.  lane_ctrl_9Lane control and assignment for Lane 9.

Offset: 0x28
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 38.  lane_ctrl_10Lane control and assignment for Lane 10.

Offset: 0x2C
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 39.  lane_ctrl_11Lane control and assignment for Lane 11.

Offset: 0x30
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 40.  lane_ctrl_12Lane control and assignment for Lane 12.

Offset: 0x34
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 41.  lane_ctrl_13Lane control and assignment for Lane 13.

Offset: 0x38
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 42.  lane_ctrl_14Lane control and assignment for Lane 14.

Offset: 0x3C
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 43.  lane_ctrl_15Lane control and assignment for Lane 15.

Offset: 0x40
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 44.  tl_ctrlTransport layer control.

Offset: 0x50

Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Table 45.  sysref_ctrlSYSREF control.

Offset: 0x54

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:16 Reserved Reserved RV 0x0
15:8 lemc_offset

Upon the detection of the rising edge of SYSREF in continuous mode or single detect mode, the LEMC counter will be reset to the value set in lemc_offset.

LEMC counter operates in link clock domain, therefore the legal value for the counter is from 0 to (E*16)-1.
  • In the event that (E*16)-1 > 255, the design has no capability to adjust the LEMC for offset greater than 255.
  • If (E*16-1) < 255, and an out-of-range value is set, the LEMC offset will be internally reset to 0.
Note: By default, the rising edge of SYSREF resets the LEMC counter to 0. However, if the system design has a large phase offset between the SYSREF sampled by the converter device and the FPGA, you can virtually shift the SYSREF edges by changing the LEMC offset reset value using this register.
RW Compile-time specific
7:3 Reserved Reserved RV 0x0
2 sysref_singledet

This register enables LEMC realignment with a single sample of the rising edge of SYSREF. The bit is auto-cleared by the hardware once SYSREF is sampled. If you require SYSREF to be sampled again (due to link reset or reinitialization), you must set this bit again.

This register also has another critical function. The JESD204C IP will never send EoEMB unless at least a SYSREF edge is sampled. This is to prevent race condition between SYSREF being sampled at RX (converter device) and the deterministic timing of EoEMB transmission.

  • 0 = Any rising edge of SYSREF will not reset the LEMC counter.
  • 1 = Resets the LEMC counter on the first rising edge of SYSREF and then clears this bit. (Default)
Note:
Intel recommends that you use sysref_singledet with sysref_alwayson even if you want to do SYSREF continuous detection mode. This is because this register is able to indicate whether SYSREF was ever sampled. This register also prevents race condition as mentioned above. Using only SYSREF single detect mode will not be able to detect incorrect SYSREF period.
RW1S 0x1
1 sysref_alwayson

This register enables LEMC realignment at every rising edge of SYSREF. LEMC counter resets when every SYSREF transition from 0 to 1 is detected.

  • 0 = Any rising edge of SYSREF will not reset the LEMC counter.
  • 1 = Continuously resets LEMC counter at every SYSREF rising edge.
Note: When this bit is set, the SYSREF period will be checked that it never violates internal extended multiblock period and this period can only be n-integer multiplied of (E*32). If the SYSREF period is different from the local extended multiblock period, the IP asserts the sysref_lemc_err (0x60) register and triggers an interrupt.
If you want to change the SYSREF period, this bit should be set to 0 first. After SYSREF clock has stabilized, this bit is set to 1 to sample the rising edges of the new SYSREF. 		RW 0x0
0 link_reinit

The JESD204C IP reinitializes the TX link by resetting all internal pipestages and status, but not including SYSREF detection information.

This bit automatically clears once link reinitialization is entered by hardware.

  • 0 = No link reinitialization request (Default)
  • 1 = Reinitialize the link.
RW1S 0x0
Table 46.  tx_errThis register logs errors detected in the FPGA IP. Each set bit in the register will generate an interrupt, if enabled by corresponding bits in the TX Error Enable register (tx_err_enable (0x64)). After servicing the interrupt, the software must clear the appropriate serviced interrupt status bit and ensure that no other interrupts are pending.

Offset: 0x60
Bit Name Description Attribute Reset
31:9 Reserved Reserved RV 0x0
8 tx_gb_overflow_err Assert when overflow happens on any of the lane’s TX gearbox. RW1C 0x0
7 tx_gb_underflow_err Assert when underflow happens on any of the lane’s TX gearbox. RW1C 0x0
6 Reserved Reserved RV 0x0
5 pcfifo_full_err

Detected 1 or more lanes of Phase Compensation FIFO is full unexpectedly when JESD204C link is running.

Note: User MUST reset JESD204C link if this bit is triggered. The transceiver channel, and the JESD204C IP core link reset must be applied.
RW1C 0x0
4 tx_ready_err Detected 1 or more lanes of tx_ready (from the transceiver) drop when the JESD204C link is running. RW1C 0x0
3 cmd_invalid_err This error bit is applicable only if Command Channel is used in the JESD204C link. This error bit will be asserted if the upstream component deassert the j204c_tx_cmd_valid signal while Link Layer is requesting for command (via j204c_tx_cmd_ready). RW1C 0x0
2 frame_data_invalid_err This error bit is applicable only if you use Intel FPGA transport layer in your design. This error bit will be asserted if the upstream component deasserts j204c_tx_avst_valid signal at the Intel FPGA transport layer Avalon-ST bus.

The transport layer expects the upstream device in the system will always send the valid data with zero latency when j204c_tx_avst_ready is asserted by the transport layer.

RW1C 0x0
1 dll_data_invalid_err This error bit will be asserted if the link layer TX detects data invalid on the Avalon-ST bus when data is requested.

By design, the JESD204C TX link layer expects the upstream device (JESD204C transport layer) will always send the valid data with zero latency when ready is asserted.

RW1C 0x0
0 sysref_lemc_err When the sysref_ctrl (0x54) sysref_alwayson register is set to 1, the LEMC counter will check whether SYSREF period matches the LEMC counter where it is n-integer multiplier of the (E*32). If SYSREF period does not match the LEMC period, this bit will be asserted. RW1C 0x0
Table 47.  tx_err_enThis register enables the error types that will generate interrupt. Setting 0 to the register bits will disable the specific error type from generating interrupt.

Offset: 0x64
Bit Name Description Attribute Reset
31:9 Reserved Reserved RV 0x0
8 tx_gb_overflow_err_en TX gearbox overflow error interrupt enable RW 0x1
7 tx_gb_underflow_err_en TX gearbox underflow error interrupt enable RW 0x1
6 Reserved Reserved RV 0x0
5 pcfifo_full_err_en PCFIFO full error interrupt enable RW 0x1
4 tx_ready_err_en Transceiver TX Ready error interrupt enable RW 0x1
3 cmd_invalid_err_en Command invalid error interrupt enable RW 0x0
2 frame_data_invalid_err_en Frame data invalid error interrupt enable RW 0x0
1 dll_data_invalid_err_en Link data invalid error interrupt enable RW 0x0
0 sysref_lemc_err_en SYSREF LEMC error interrupt enable RW 0x1
Table 48.  tx_err_link_reinitThis register enables the error types that will generate link reinitialization. Setting 0 to the register bits will disable the specific error type from link reinitialization.

Offset: 0x68
Bit Name Description Attribute Reset
31:9 Reserved Reserved RV 0x0
8 tx_gb_overflow_err_en_reinit TX gearbox overflow error reinitialization enable. RW 0x0
7 tx_gb_underflow_err_en_reinit TX gearbox underflow error reinitialization enable. RW 0x0
6 Reserved Reserved RV 0x0
5 pcfifo_full_err_en_reinit

PCFIFO full error reinitialization enable.

Note: Link reinitialization sequence does not cover the transceiver reinitialization steps, hence such error will not be recovered via link reinit.
RW 0x0
4 tx_ready_err_en_reinit

Transceiver TX ready error reinitialization enable.

Note: Link reinitialization sequence does not cover transceiver reinitialization steps, hence such error will not be recovered via link reinitialization.
RW 0x0
3 cmd_invalid_err_en_reinit Command invalid error reinitialization enable RW 0x0
2 frame_data_invalid_err_en_reinit Frame data invalid error reinitialization enable RW 0x0
1 dll_data_invalid_err_en_reinit Link data invalid error reinitialization enable RW 0x0
0 sysref_lemc_err_en_reinit SYSREF LEMC error reinitialization enable RW 0x0
Table 49.  tx_status0Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x80

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:12 Reserved Reserved RV 0x0
11 sysref_det_pending Indicate that SYSREF is yet to be detected. You need to set the sysref_singledet bit to enable link initialization. ROV 0x0
10 reinit_in_prog Indicates that auto or manual link reinitialization is in progress. ROV 0x0
9:2 lemc_period Represent E: the number of multiblock in an extended multiblock. RO Compile-time specific
1:0 sh_config

Sync header encoding configuration

b00: CRC-12

b01: Standalone command channel

b10: Reserved

b11: Reserved

 RO Compile-time specific
Table 50.  tx_status1Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x84
Bit Name Description Attribute Reset
31:16 Reserved Reserved RV 0x0
15 lane15_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 15 ROV 0x0
14 lane14_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 14 ROV 0x0
13 lane13_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 13 ROV 0x0
12 lane12_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 12 ROV 0x0
11 lane11_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 11 ROV 0x0
10 lane10_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 10 ROV 0x0
9 lane9_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 9 ROV 0x0
8 lane8_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 8 ROV 0x0
7 lane7_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 7 ROV 0x0
6 lane6_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 6 ROV 0x0
5 lane5_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 5 ROV 0x0
4 lane4_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 4 ROV 0x0
3 lane3_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 3 ROV 0x0
2 lane2_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 2 ROV 0x0
1 lane1_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 1 ROV 0x0
0 lane0_tx_pcfifo_full TX phase compensation FIFO status full flag for Lane 0 ROV 0x0
Table 51.  tx_status2Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x88
Bit Name Description Attribute Reset
31:16 Reserved Reserved RV 0x0
15 lane15_tx_xcvr_ready TX transceiver ready status flag for Lane 15 ROV 0x0
14 lane14_tx_xcvr_ready TX transceiver ready status flag for Lane 14 ROV 0x0
13 lane13_tx_xcvr_ready TX transceiver ready status flag for Lane 13 ROV 0x0
12 lane12_tx_xcvr_ready TX transceiver ready status flag for Lane 12 ROV 0x0
11 lane11_tx_xcvr_ready TX transceiver ready status flag for Lane 11 ROV 0x0
10 lane10_tx_xcvr_ready TX transceiver ready status flag for Lane 10 ROV 0x0
9 lane9_tx_xcvr_ready TX transceiver ready status flag for Lane 9 ROV 0x0
8 lane8_tx_xcvr_ready TX transceiver ready status flag for Lane 8 ROV 0x0
7 lane7_tx_xcvr_ready TX transceiver ready status flag for Lane 7 ROV 0x0
6 lane6_tx_xcvr_ready TX transceiver ready status flag for Lane 6 ROV 0x0
5 lane5_tx_xcvr_ready TX transceiver ready status flag for Lane 5 ROV 0x0
4 lane4_tx_xcvr_ready TX transceiver ready status flag for Lane 4 ROV 0x0
3 lane3_tx_xcvr_ready TX transceiver ready status flag for Lane 3 ROV 0x0
2 lane2_tx_xcvr_ready TX transceiver ready status flag for Lane 2 ROV 0x0
1 lane1_tx_xcvr_ready TX transceiver ready status flag for Lane 1 ROV 0x0
0 lane0_tx_xcvr_ready TX transceiver ready status flag for Lane 0 ROV 0x0
Table 52.  tx_converter_param1Link and transport control configuration per converter parameters.

Offset: 0xC0

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:30 CS Number of control bits per converter sample. 1-based value. For example, 0=0 bit, 1=1 bit. RO Compile-time specific
29 HD High Density format. RO Compile-time specific
28:24 N

Number of data bits per converter sample. 0-based value. For example, 0=1 bit, 1=2 bits.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

RO Compile-time specific
23:16 M

Number of converter per device. 0-based value. For example, 0=1 converter, 1=2 converters.

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
15:8 F

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.Number of octets per frame. 0-based value. For example, 0=1 octet, 1=2 octets.
RO Compile-time specific
7:4 Reserved Reserved RV 0x0
3:0 L

Number of lanes per link. 0-based value. For example, 0=1 lane, 1=2 lanes.

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
Table 53.  tx_converter_param2Link and transport control configuration per converter parameters.

Offset: 0xC4

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:24 E

Number of multiblock within an extended multiblock. 0-based value. For example, 0=1 multiblock to form extended multiblock, 1=2 multiblock to form an extended multiblock.

If (256 Mod F)=1, E must be greater than 1. (The register value should be greater than 0).

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
23:21 Reserved Reserved RV 0x0
20:16 CF Number of control words per frame clock per link. 1-based value. I.e 0=0 word, 1=1 word. RO Compile-time specific
15:13 Reserved Reserved RV 0x0
12:8 S

Number of samples per converter frame cycle. 0-based value. For example, 0=1 sample, 1=2 samples.

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
7:5 subclass_ver

Device Subclass Version

  • b000: Subclass 0
  • b001: Subclass 1
 RO Compile-time specific
4:0 NP

Number of data bits+control bits+tail bits per converter sample. 0-based value. For example, 0=1 bit, 1=2 bits.

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
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