JESD204C Intel® FPGA IP User Guide

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ID 683108
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel FPGA IP User Guide 2. Overview of the JESD204C Intel FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the JESD204C Intel® FPGA IP 6. JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the JESD204C Intel® FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. JESD204C Intel® FPGA IP Features 2.4. Presets 2.5. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the JESD204C Intel® FPGA IP x
5.1. JESD204C TX and RX Reset Sequence 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the JESD204C Intel FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the JESD204C Intel® FPGA IP
6. JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the JESD204C Intel® FPGA IP User Guide

10. Document Revision History for the JESD204C Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.06.26 23.2 3.1.0 Updated the ordering code in Table: JESD204C Intel® FPGA IP Release Information.
2023.02.10 21.3 1.1.0
  • Fixed the links in Table 1: Related Documents.
  • Updated the JESD204C Intel® FPGA IP User Guide Archives section.
2021.10.22 21.3 1.1.0
  • Updated the description for Control and Status Registers clarify that registers that are Read-Writable must be protected to comply with Security Development Lifecycle (SDL) practices.
  • Updated information about bit[31:16] in Table: rx_status4.
  • Updated Table: Brief Information about the JESD204C Intel® FPGA IP to include support for QuestaSim* simulator.
  • Updated the description for Frame clock frequency multiplier (FCLK_MULP) in Table: JESD204C Intel® FPGA IP Parameters.
2021.06.16 21.2 1.1.0
  • Removed NCSim support from the list of design tools in Table: Brief Information about the JESD204C Intel® FPGA IP .
  • Updated the description for TX/RX device clock in Table: JESD204C IP Clocks.
  • Added information about the reference clocks of the transceiver and core PLLs in the Device Clock section.
2021.03.12 20.1 1.1.0 Updated Table: rx_err_link_reinit to correct the bit 0 name from syncref_lemc_err_en_reinit to sysref_lemc_err_en_reinit.
2020.10.05 20.1 1.1.0 Corrected the description for sampling SYSREF in the Local Extended Multiblock Clock section. The IP uses the link clock to sample SYSREF, not the frame clock.
2020.05.04 20.1 1.1.0
  • Added Device Family Support section.
  • Updated the supported data rate for the different fabric speed grades for Intel Agilex® 7 and Intel® Stratix® 10 devices in the Performance and Resource Utilization section.
  • Added information about the new Multilink mode parameter in the JESD204C Intel® FPGA IP Parameters section.
  • Added a note for the Frame data width multiplier (WIDTH_MULP) parameter in the JESD204C Intel® FPGA IP Parameters section. Select the smallest data width multiplier value on the list. Other data width multiplier values are not allowed.
  • Edited the range of values supported for the Control bits (CS) parameter.
  • Added information about the following two new signals for multilink mode in the Receiver Signals section:
    • j204c_rx_dev_emblock_align
    • j204c_rx_alldev_emblock_align
2019.12.16 19.4 1.1.0
  • Updated the supported maximum data rate to 28.9 Gbps (for Intel Agilex® 7 devices) in the Overview of the JESD204C Intel® FPGA IP , JESD204C Intel® FPGA IP Features, and Functional Description sections.
  • Updated the resource utilization data for Intel® Stratix® 10 and Intel Agilex® 7 devices, and the supported maximum data rate to 28.9 Gbps for Intel® Stratix® 10 and Intel Agilex® 7 devices in the Performance and Resource Utilization section.
  • Updated the maximum data rate value option to 28.9 Gbps for the Data Rate parameter in the JESD204C Intel® FPGA IP Parameters section.
  • Added a note to set specific data rates when the frame clock multiplier is 2 in the description for the Frame clock frequency multiplier (FCLK_MULP) parameter in the JESD204C Intel® FPGA IP Parameters section.
  • Added a note to insert 2 pipeline stages for high data rates in the description for the parameter in the JESD204C Intel® FPGA IP Parameters section.
  • Removed the Validated VariantsEnable TX pipestage (Transmitter) table.
2019.10.23 19.3 1.0.0
  • Added advance support for Intel Agilex® 7 devices.
  • Updated the related document links and the acronyms, glossary, and symbols lists in the About the JESD204C Intel® FPGA IPEnable TX pipestage User Guide section.
  • Updated the JESD204C Intel® FPGA IP Features section with maximum data rate information for Intel Agilex® 7 devices.
  • Updated the Performance and Resource Utilization section with Intel Agilex® 7 devices information.
  • Edited the maximum SYSREF frequency calculation in the LEMC Counter section for clarity.
2019.07.05 19.2 1.0.0 Initial release.
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