PHY Lite for Parallel Interfaces FPGA IP Cores Release Notes

ID 683090
Date 3/31/2025
Public
Document Table of Contents

PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v7.0.0

Table 3.  v7.0.0 2024.11.18
Quartus® Prime Version Description Impact
24.3
  • Cal IP refactoring. Added RX FIFO delay and D0DlyRange registers.
  • POD inputs are now allowed with RZQ.
  • GUI IP parameters have been updated.
Altera requires that you regenerate your IP.