PHY Lite for Parallel Interfaces FPGA IP Cores Release Notes

ID 683090
Date 3/31/2025
Public
Document Table of Contents

PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v6.0.0

Table 4.  v6.0.0 2024.07.08
Quartus® Prime Version Description Impact
24.2
  • Changed the default value of the GROUP_X_RCVEN_TO_READ_VALID_OFFSET parameter.
  • Use external OSC_CLK_1 as configuration clock source.
Altera requires that you regenerate your IP.