Intel® FPGA Download Cable User Guide

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ID 683076
Date 8/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® FPGA Download Cable 2. Specifications for Intel® FPGA Download Cable 3. Using the Intel® FPGA Download Cable 4. Document Revision History for the Intel® FPGA Download Cable User Guide A. Additional Information
1. Introduction to Intel® FPGA Download Cable x
1.1. Intel® FPGA Download Cable Revision 1.2. Supported Devices and Host Systems
2. Specifications for Intel® FPGA Download Cable x
2.1. Block Diagram and Dimension 2.2. Cable-to-Board Connection 2.3. Pin Description 2.4. Operating Conditions 2.5. Power Requirements 2.6. RoHS Compliance
3. Using the Intel® FPGA Download Cable x
3.1. Installing the Intel® FPGA Download Cable Driver on Windows 3.2. Installing the Intel® FPGA Download Cable Driver on Linux 3.3. Setting up the Intel® FPGA Download Cable Hardware in the Quartus® Prime Software 3.4. Connecting the Intel® FPGA Download Cable to the Board
3.2. Installing the Intel® FPGA Download Cable Driver on Linux x
3.2.1. Installing on Red Hat Enterprise 4 or Earlier Versions 3.2.2. Installing on Red Hat Enterprise Linux 6 and Above, and Ubuntu Versions 18, 20, and 22
A. Additional Information x
A.1. Windows Troubleshooting Procedure for Intel® FPGA Download Cable A.2. Troubleshooting Procedure for Error when scanning hardware - No Devices
A.1. Windows Troubleshooting Procedure for Intel® FPGA Download Cable x
A.1.1. Jtagconfig version setting ( Quartus® Prime software root directory setting) A.1.2. Jtagserver Setting A.1.3. Install/Reinstall the Intel® FPGA Download Cable Driver
A.1.1. Jtagconfig version setting ( Quartus® Prime software root directory setting) x
A.1.1.1. Automatic Setting A.1.1.2. Manual Setting
1. Introduction to Intel® FPGA Download Cable
2. Specifications for Intel® FPGA Download Cable
3. Using the Intel® FPGA Download Cable
4. Document Revision History for the Intel® FPGA Download Cable User Guide
A. Additional Information

2.3. Pin Description

The following table lists the pins of the Intel® FPGA Download Cable female plug and describes their functions in the JTAG, active serial and passive serial modes.

Table 3.  Signal Names of the Intel® FPGA Download Cable Female Plug
Pin AS Mode PS Mode JTAG Mode
Signal Name Description Signal Name Description Signal Name Description
1 DCLK Clock signal. DCLK Clock signal. TCK Clock signal.
2 GND Signal ground. GND Signal ground. GND Signal ground.
3 CONF_DONE Configuration done. CONF_DONE Configuration done. TDO Data from device.
4 VCC(TRGT) Target power supplied by the device board. VCC(TRGT) Target power supplied by the device board. VCC(TRGT) Target power supplied by the device board.
5 nCONFIG Configuration control. nCONFIG Configuration control. TMS JTAG state machine control.
6 nCE Cyclone chip enable. — — — —
7 DATAOUT Active serial data out. nSTATUS Configuration status. — —
8 nCS Serial configuration device chip select. — — — —
9 ASDI Active serial data in. DATA0 Data to device. TDI Data to device.
10 GND Signal ground. GND Signal ground. GND Signal ground.
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