Intel® FPGA Download Cable User Guide

ID 683076
Date 3/11/2020
Public
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Document Table of Contents

2.3. Pin Description

The following table lists the pins of the Intel® FPGA Download Cable female plug and describes their functions in the JTAG, active serial and passive serial modes.

Table 3.  Signal Names of the Intel® FPGA Download Cable Female Plug
Pin AS Mode PS Mode JTAG Mode
Signal Name Description Signal Name Description Signal Name Description
1 DCLK Clock signal. DCLK Clock signal. TCK Clock signal.
2 GND Signal ground. GND Signal ground. GND Signal ground.
3 CONF_DONE Configuration done. CONF_DONE Configuration done. TDO Data from device.
4 VCC(TRGT) Target power supplied by the device board. VCC(TRGT) Target power supplied by the device board. VCC(TRGT) Target power supplied by the device board.
5 nCONFIG Configuration control. nCONFIG Configuration control. TMS JTAG state machine control.
6 nCE Cyclone chip enable.
7 DATAOUT Active serial data out. nSTATUS Configuration status.
8 nCS Serial configuration device chip select.
9 ASDI Active serial data in. DATA0 Data to device. TDI Data to device.
10 GND Signal ground. GND Signal ground. GND Signal ground.

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