F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 1/14/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

2.4. Register Map

Note:
  • Design Example register address starts with 0x20** while the Interlaken IP core register address starts with 0x10**.
  • F-tile PHY register address starts with 0x30** while the F-tile FEC register address starts with 0x40**. FEC register is only available in PAM4 mode.
  • Access code: RO—Read Only, and RW—Read/Write.
  • System console reads the design example registers and reports the test status on the screen.
Table 7.  Design Example Register Map
Offset Name Access Description
8'h00 Reserved
8'h01 Reserved
8'h02 System PLL reset RO Following bits indicates system PLL reset request and enable value:
  • Bit [0] - sys_pll_rst_req
  • Bit [1] - sys_pll_rst_en
8'h03 RX lane aligned RO Indicates the RX lane alignment.
8'h04 WORD locked RO [NUM_LANES–1:0] – Word (block) boundaries identification.
8'h05 Sync locked RO [NUM_LANES–1:0] – Metaframe synchronization.
8'h06 - 8'h09 CRC32 error count RO Indicates the CRC32 error count.
8'h0A CRC24 error count RO Indicates the CRC24 error count.
8'h0B Overflow/Underflow signal RO Following bits indicate:
  • Bit [3] - TX underflow signal
  • Bit [2] - TX overflow signal
  • Bit [1] - RX overflow signal
8'h0C SOP count RO Indicates the number of SOP.
8'h0D EOP count RO Indicates the number of EOP
8'h0E Error count RO Indicates the number of following errors:
  • Loss of lane alignment
  • Illegal control word
  • Illegal framing pattern
  • Missing SOP or EOP indicator
8'h0F send_data_mm_clk RW Write 1 to bit [0] to enable the generator signal.
8'h10 Checker error   Indicates the checker error. (SOP data error, Channel number error, and PLD data error)
8'h11 System PLL lock RO Bit [0] indicates PLL lock indication.
8'h14 TX SOP count RO Indicates number of SOP generated by the packet generator.
8'h15 TX EOP count RO Indicates number of EOP generated by the packet generator.
8'h16 Continuous packet RW Write 1 to bit [0] to enable the continuous packet.
8'h39 ECC error count RO Indicates number of ECC errors.
8'h40 ECC corrected error count RO Indicates number of corrected ECC errors.
8’h50 tile_tx_rst_n WO Tile reset to SRC for TX.
8’h51 tile_rx_rst_n WO Tile reset to SRC for RX.
8’h52 tile_tx_rst_ack_n RO Tile reset acknowledge from SRC for TX.
8’h53 tile_rx_rst_ack_n RO Tile reset acknowledge from SRC for RX.
Table 8.  Design Example Register Map for Interlaken Look-aside Design ExampleUse this register map when you generate the design example with Enable Interlaken Look-aside Mode parameter turned on.
Offset Name Access Description
8'h00 Reserved
8'h01 Counter reset RO Write 1 to bit [0] to clear TX and RX counter equal bit.
8'h02 System PLL reset RO Following bits indicates system PLL reset request and enable value:
  • Bit [0] - sys_pll_rst_req
  • Bit [1] - sys_pll_rst_en
8'h03 RX lane aligned RO Indicates the RX lane alignment.
8'h04 WORD locked RO [NUM_LANES–1:0] – Word (block) boundaries identification.
8'h05 Sync locked RO [NUM_LANES–1:0] – Metaframe synchronization.
8'h06 - 8'h09 CRC32 error count RO Indicates the CRC32 error count.
8'h0A CRC24 error count RO Indicates the CRC24 error count.
8'h0B Reserved
8'h0C SOP count RO Indicates the number of SOP.
8'h0D EOP count RO Indicates the number of EOP
8'h0E Error count RO Indicates the number of following errors:
  • Loss of lane alignment
  • Illegal control word
  • Illegal framing pattern
  • Missing SOP or EOP indicator
8'h0F send_data_mm_clk RW Write 1 to bit [0] to enable the generator signal.
8'h10 Checker error RO Indicates the checker error. (SOP data error, Channel number error, and PLD data error)
8'h11 System PLL lock RO Bit [0] indicates PLL lock indication.
8'h13 Latency count RO Indicates number of latency.
8'h14 TX SOP count RO Indicates number of SOP generated by the packet generator.
8'h15 TX EOP count RO Indicates number of EOP generated by the packet generator.
8'h16 Continuous packet RO Write 1 to bit [0] to enable the continuous packet.
8'h17 TX and RX counter equal RW Indicates TX and RX counter are equal.
8'h23 Enable latency WO Write 1 to bit [0] to enable latency measurement.
8'h24 Latency ready RO Indicates latency measurement are ready.
8’h50 tile_tx_rst_n WO Tile reset to SRC for TX.
8’h51 tile_rx_rst_n WO Tile reset to SRC for RX.
8’h52 tile_tx_rst_ack_n RO Tile reset acknowledge from SRC for TX.
8’h53 tile_rx_rst_ack_n RO Tile reset acknowledge from SRC for RX.
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