A newer version of this document is available. Customers should click here to go to the newest version.
2.1. Design Example Components
The example design connects system and PLL reference clocks and required design components. The example design configures the IP core in internal loopback mode and generates packets on the IP core TX user data transfer interface. The IP core sends these packets on the internal loopback path through the transceiver.
After the IP core receiver receives the packets on the loopback path, it processes the Interlaken packets and transmits them on the RX user data transfer interface. The example design checks that the packets received and transmitted match.
- F-Tile Interlaken Intel® FPGA IP core
- Packet Generator and Packet Checker
- F-Tile Reference and System PLL Clocks Intel® FPGA IP core
Did you find the information on this page useful?