Intel® Acceleration Stack v2.0.1 Features
Feature | Description |
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Security Enhancements |
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CCI-P Byte Enable | Supports programmable byte writes less than 1 cache line in length. Refer to the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual for more details. |
Networking Interface |
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Sample AFUs Supported | The following unsigned AFU examples are provided with the Intel Acceleration Stack for Intel Xeon CPU with FPGAs:
Note: Each *_unsigned.gbs above is prepended with the necessary block0 and block1 headers but there are no hashes in these headers that have been signed with the root and code signing keys. To learn how to securely sign a provided *_unsigned.gbs refer to the Intel® Acceleration Stack Quick Start Guide: Intel FPGA Programmable Acceleration Card D5005 .
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