Acceleration Acronym List

Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0.1 Release Notes: For the Intel FPGA Programmable Acceleration Card D5005

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ID 683046

Date 6/14/2021

Version 2.0.1

Public

Acceleration Acronym List

Use the following table as a reference when reviewing the release notes.

Table 1. Acronyms
Acronyms	Expansion	Description
AFU	Accelerator Functional Unit	Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.
AF	Accelerator Function	Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application. An AFU and associated AFs may also be referred to as GBS (Green-Bits, Green BitStream) in the Acceleration Stack installation directory tree and in source code comments.
ASE	AFU Simulation Environment	Co-simulation environment that allows you to use the same host application and AF in a simulation environment. ASE is part of the Intel Acceleration Stack for FPGAs.
FIM	FPGA Interface Manager	The FPGA component containing the FPGA Interface Unit (FIU) and external interfaces for memory, networking, etc. The FIM may also be referred to as BBS (Blue-Bits, Blue BitStream) in the Acceleration Stack installation directory tree and in source code comments. The Accelerator Function (AF) interfaces with the FIM at run time.
HSSI	High-speed Serial Interface	Reference to the multi-gigabit serial transceiver I/O in the FIM and the corresponding interface to the Accelerator Functional Unit (AFU).
OPAE	Open Programmable Acceleration Engine	The OPAE is a software framework for managing and accessing AFs.
PIM	Platform Interface Manager	An abstraction layer for managing top-level device ports and system-provided clock crossing.
PR	Partial Reconfiguration	The ability to dynamically reconfigure a portion of an FPGA while the remaining FPGA design continues to function.