Ethernet Design Example Components User Guide

Download PDF
ID 683044
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

3.2. Resource Utilization

Table 27.  Estimated Resource Utilization in Arria® 10 Devices (10AX115U2F45I2SGES)
Configuration ALMs Combinational ALUTs Logic Registers Memory

(M20K Blocks)
Default Mode 212 297 179 8
Table 28.  Estimated Resource Utilization in Stratix® 10 Devices (1SX280LN2F43E2LG)
Configuration ALMs Combinational ALUTs Logic Registers Memory

(M20K Blocks)
Default Mode 292 332 533 9
Table 29.  Estimated Resource Utilization in Agilex™ 7 Devices (AGFB014R24A2E2V)
Configuration ALMs Combinational ALUTs Logic Registers Memory

(M20K Blocks)
Default Mode 498 339 223 8
Table 30.  Estimated Resource Utilization in Agilex™ 5 Devices (A5EC065BB32AE6S)
Configuration ALMs Combinational ALUTs Logic Registers Memory

(M20K Blocks)
Default Mode 496 340 217 8
Level Two Title