Ethernet Design Example Components User Guide

ID 683044
Date 9/27/2021

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1.5.4. Clocking Requirements

  • Expect the clk frequency to be equal or less than 100 MHz.
  • The period_clk must have the same clock source as the timestamping consumer, e.g. MAC. In case the frequency exceeds 156.25 MHz, when OFFSET_JITTER_WANDER_EN is enabled, use the ToD in conjunction with the TOD Synchronizer.
  • Set the pps_sampling_clk frequency as close as possible to the formula given in the interface description per . Deviation from the formula can impact the accuracy of the PPS signal.
  • Set the iopll_scan_clk with any value between 50 MHz and 100 MHz. The lower frequency of the scanclk, the longer the IOPLL takes to carry out the phase shift operation.