P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683038
Date 10/02/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.6.1. Running the PIO Design Example

  1. Navigate to ./software/user/example under the design example directory.
  2. Compile the design example application:

    $ make

  3. Run the test:

    $ sudo ./intel_fpga_pcie_link_test

    You can run the Intel® FPGA IP PCIe* link test in manual or automatic mode. Choose from:
    • In automatic mode, the application automatically selects the device. The test selects the Intel PCIe* device with the lowest BDF by matching the Vendor ID. The test also selects the lowest available BAR.
    • In manual mode, the test queries you for the bus, device, and function number and BAR.

    For the Intel® Stratix® 10 DX or Intel Agilex® 7 Development Kit, you can determine the BDF by typing the following command:

    $ lspci -d 1172:

  4. Here are sample transcripts for automatic and manual modes:

    Automatic mode:

Manual mode: