P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683038
Date 4/10/2023
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Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples x
1.1. Overview 1.2. Functional Description for the Programmed Input/Output (PIO) Design Example 1.3. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.4. Functional Description for the Performance Design Example 1.5. Hardware and Software Requirements
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulations 2.3.2. Testbench
2.3.1. Steps to Run Simulations x
2.3.1.1. Running Simulations Using QuestaSim* 2.3.1.2. Running Simulations Using VCS* 2.3.1.3. Running Simulations Using Riviera*
2.3.2. Testbench x
2.3.2.1. Test Driver Module 2.3.2.2. PIO Design Example Testbench 2.3.2.3. SR-IOV Design Example Testbench 2.3.2.4. Performance Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example 2.6.3. Running the Performance Design Example
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

2.3.1.2. Running Simulations Using VCS*

To run simulations using the VCS* simulator, follow these steps:

  1. Go to the working directory <example_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcs.
  2. Type sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final\ -debug_all" USER_DEFINED_SIM_OPTIONS="" | tee simulation.log
    Note: The command above is a single-line command.
  3. A successful simulation ends with the following message, "Simulation stopped due to successful completion!".
    Note:
    To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in non-interactive mode, delete the simv and simv.diadir)
    1. Open the vcs_setup.sh file and add a debug option to the VCS command: vcs -debug_access+all.
    2. Compile the design example: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" SKIP_SIM=1.
    3. Start the simulation in interactive mode: simv -gui &.
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