P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Download PDF
ID 683038
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples x
1.1. Overview 1.2. Functional Description for the Programmed Input/Output (PIO) Design Example 1.3. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.4. Functional Description for the Performance Design Example 1.5. Hardware and Software Requirements
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulations 2.3.2. Testbench
2.3.1. Steps to Run Simulations x
2.3.1.1. Running Simulations Using QuestaSim* 2.3.1.2. Running Simulations Using VCS* 2.3.1.3. Running Simulations Using Riviera*
2.3.2. Testbench x
2.3.2.1. Test Driver Module 2.3.2.2. PIO Design Example Testbench 2.3.2.3. SR-IOV Design Example Testbench 2.3.2.4. Performance Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example 2.6.3. Running the Performance Design Example
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

2.3.1.1. Running Simulations Using QuestaSim*

From the Intel® Quartus® Prime 22.3 release onward, use the QuestaSim* 2022.3 version.

To run simulations using the Siemens EDA QuestaSim* or Questa Intel® FPGA Edition simulators, follow these steps:

  1. Go to the working directory <example_design>/pcie_ed_tb/pcie_ed_tb/sim/mentor/.
  2. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  3. Type: do msim_setup.tcl
    Note: Alternatively, instead of doing Steps 2 and 3, you can type: vsim -c -do msim_setup.tcl.
  4. Type: ld_debug
  5. Type: run -all
  6. A successful simulation ends with the following message, "Simulation stopped due to successful completion!".
Level Two Title