- 1.3. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition and Cyclone® V SoC Development Kit Setup Processes
1.5. Cyclone V SoC Development Kit Reference Platform Board Variants
- c5soc board
This default board provides access to two DDR memory banks. The HPS DDR is accessible by both the FPGA and the CPU. The FPGA DDR is only accessible by the FPGA.
- c5soc_sharedonly board
This board variant contains only HPS DDR connectivity. The FPGA DDR is not accessible. This board variant is more area efficient because less hardware is necessary to support one DDR memory bank. The c5soc_sharedonly board is also a good prototyping platform for a final production board with a single DDR memory bank.
To target this board variant when compiling your OpenCL kernel, include the -board=c5soc_sharedonly option in your aoc command.
For more information about the -board=<board_name> option of the aoc command, refer to the Intel® FPGA SDK for OpenCL™ Standard Edition Programming Guide.
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