F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 6/20/2022
Public

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4.4.7. Reference Time Interval

Table below displays the number of bits between two subsequent reference time captures. The UI adjustment calculation uses these numbers. To speed up the simulation, the number for simulation is smaller.
Table 17.  Reference Time (TAM) Interval
FEC type:
  • No FEC: No FEC
  • CL74: IEEE 802.3 BASE-R Firecode (CL74)
  • CL91: IEEE 802.3 RS(528,514) (CL91)
  • CL134: IEEE 802.3 RS(544,514) (CL134)
  • ETC: Ethernet Technology Consortium ETC RS(272, 258)
Mode FEC Type Simulation (bit) Hardware (bit)
TX RX 14 TX RX
10GE No FEC 168,960 168,960 5,406,720 168,960
25GE No FEC 168,960 168,960 5,406,720 168,960
CL74
CL91 168,960 168,960 5,406,720 5,406,720
50GE No FEC (ETC) 337,920 337,920 4,325,376 4,325,376
CL91 337,920 337,920 5,406,72 5,406,720
CL134
ETC
100GE No FEC 675,840 675,840 21,626,880 21,626,880
CL91
CL134
ETC
200GE CL134 1,351,680 1,351,680 21,626,880 21,626,880
ETC
400GE CL134 2,703,360 2,703,360 43,253,760 43,253,760
ETC
14 Depends on the link partner AM. The numbers assume serial loopback.