F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 6/20/2022
Public

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7.12. Deterministic Latency Interface

The F-Tile Ethernet Intel® FPGA Hard IP Deterministic Latency Interface ports are available when you turn on Include deterministic latency measurement interface in FlexE mode using the IP Parameter Editor.

Use the deterministic latency interface if you want to precisely measure the latency along the TX/RX datapaths. It compares the arrival time of a known digital bit (typically the start of an alignment marker) with the arrival time of an analog pulse generated at the same point.

The table below depicts the deterministic latency interface ports that are exposed to the user when the FlexE mode is turned on.
Figure 49. Enable Deterministic Latency Interface IP Parameter Editor
Note: You cannot enable the Deterministic Latency Interface and PTP interface at the same time.
Table 52.  Signals of the Deterministic Latency InterfaceAll of the Deterministic Latency Interface signals are asynchronous. The width <n> in this table refers to the number of transceivers required for the Ethernet port.

Signal Name

Width

Description

o_tx_dl_async_pulse[n-1:0] <n>

Asynchronous output latency pulse from TX datapath.

o_rx_dl_async_pulse[n-1:0] <n>

Asynchronous output latency pulse from RX datapath.

i_latency_sclk[n-1:0] <n>

Asynchronous latency calibration pulse input.

i_tx_dl_measure_sel[n-1:0] <n>
Mux select signal for the TX path.
  • 0 is for the wire delay.
  • 1 is for the datapath latency.
i_rx_dl_measure_sel[n-1:0] <n>
Mux select signal for the RX path.
  • 0 is for the wire delay.
  • 1 is for the datapath latency.