F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 6/20/2022
Public

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9.1.3. Functional Description

Figure 59. F-Tile Auto-Negotiation and Link Training Intel FPGA IP Block Diagram

Nios® CPU subsystem executes the AN/LT firmware. CSR blocks provide interface to the client logic.

Once configured and brought out of reset, the AN/LT functionality is automatic. To ensure the autoconnection expected behavior, connect anlt_link port from F-tile AN/LT IP to the Ethernet IP.

Based on configuration, the F-tile AN/LT IP begins the auto-negotiation and link training flows and the Ethernet IP function is temporarily disabled. Once AN/LT is complete, the Ethernet IP re-enables into a data mode and behaves as a standard Ethernet port. Depending on the configuration, if the RX Ethernet link goes down, the AN/LT IP may restart the auto-negotiation flow.

You can access the F-tile AN/LT IP CSR registers at any time to monitor status, change configuration, or interrupt or restart the flow for any of the Ethernet ports connected to that AN/LT IP instance.