Port SYCL* with oneAPI DPC++ to XILINX* FPGA


Many accelerators come with programming environments that are suitable for electrical engineers or for use with machine learning frameworks, but remain difficult to use in the context of high-performance computing (HPC).

SYCL* 2020 can bring direct programming for various accelerators through the concept of generic back ends.

We port the open-source oneAPI DPC++ implementation to XILINX ALVEO* FPGA cards and also target the XILINX VERSAL* ACAP CGRA with 400 VLIW vector processors.

We extend SYCL with collaborative operations to use the distributed memory shared by the 2D processor neighborhood, which is useful for stencil code.


Ronan Keryell is a principal software engineer at XILINX Research Labs and is the specification editor of the SYCL standard. He discovered the superpower of modern C++ and SYCL for CPU and GPU while working at AMD* and now is extending SYCL benefits to other hardware accelerators like FPGA and CGRA.



Product and Performance Information


Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.