Introduction to oneAPI and the Intel® Developer Cloud
Introduction to oneAPI and the Intel® Developer Cloud
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Overview
oneAPI is a productive, smart path to freedom for accelerated computing that delivers a unified programming model for development across diverse architectures. It includes:
- Unified and simplified languages
- Libraries for expressing parallelism delivering uncompromising built-in high-level language performance across a range of hardware including CPUs, GPUs, and FPGAs
This workshop is for developers with a foundational knowledge of C or C++, FPGA, and GPU programming.
In this workshop, Praveen Kundurthy (a developer evangelist from Intel for AI and oneAPI) covers:
- How oneAPI can solve the challenges of programming in a heterogeneous world
- The SYCL* language for high-performance computing (HPC) applications and oneAPI programming model
- How to use SYCL buffers and accessors for data and memory management between host and device
- The basics of graphs and dependences in SYCL
- Test-drive Intel® tools and libraries in the Intel® Developer Cloud
- How to get familiar with using a Jupyter* Notebook on Intel Developer Cloud for hands-on training through simple SYCL code examples
Highlights
0:00 Introductions
2:16 Agenda
3:05 Learning objectives
3:47 Programming challenges for multiple architectures
4:45 Introducing oneAPI
5:53 Intel® toolkits
7:15 Intel® oneAPI Base Toolkit
9:20 Intel® DPC++ Compatibility Tool
10:28 Intel® VTune™ Profiler
11:19 Intel® Advisor
14:10 Set up Intel Developer Cloud and Jupyter* environments
19:20 SYCL essentials course
20:04 What is the oneAPI implementation of SYCL?
21:10 A complete SYCL program example
24:13 Buffer memory model
28:17 Submit to a device
29:35 Important classes in SYCL
31:25 Accessor modes
32:10 Parallel kernels
33:35 Basic parallel kernels
34:32 ND-Range kernels
37:09 SYCL code anatomy
41:18 Buffer: sub_buffers
43:40 sub_buffers example continued
45:39 Asynchronous execution
49:20 Synchronization: Host accessors
50:40 Synchronization: Buffer destruction
51:45 Custom device selector
53:35 Hands-on lab
1:05:08 Module 2
1:15:15 Execution graph scheduling
1:16:10 Read after write (RAW)
1:17:45 Write after read and write after write
1:19:18 Linear dependency chain graphs and Y pattern graphs
1:20:20 Linear dependence using in-order queue example
1:21:45 Y pattern using an example of in-order queues
1:23:03 Recap of workshop
Develop performant code quickly and correctly across hardware targets, including CPUs, GPUs, and FPGAs, with this standards-based, multiarchitecture compiler.
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