F-Tile Auto-Negotiation and Link Training Intel® FPGA IP Register Map

Download

FPGA Documentation Index Agilex™ 7 M-Series FPGA and SoC FPGA Support Agilex™ 7 I-Series FPGA and SoC FPGA Support Agilex™ 7 FPGAs and SoC FPGAs Support

637460
2025-01-22
Public

Description

Register Map for the F-Tile Auto-Negotiation and Link Training Intel® FPGA IP, which contains a hardened AN/LT protocol stack and synthesizable soft logic. It supports up to 25Gbps data rate with various RS-FEC types.

Usage instructions