Visible to Intel only — GUID: sbu1520273788966
Ixiasoft
Visible to Intel only — GUID: sbu1520273788966
Ixiasoft
10.6.1. Reset Recommendations
In traditional FPGA RTL for non- Intel® Stratix® 10 devices, it is common practice to reset every register indiscriminately for easy implementation without negative effects on performance. However, to improve the performance of your Intel® Stratix® 10 design, you must minimize the number of resets.
Avoid unnecessary resets in your Intel® Stratix® 10 design for the following reasons:
- The resulting high-fanout signal prevents the Intel® Quartus® Prime Pro Edition software's retimer to find a satisfactory solution.
For more in-depth explanation, refer to the Avoid Broadcast Signals section in the Intel® Stratix® 10 High-Performance Design Handbook. Note that the term "broadcast signals" refers to high-fanout signals.
- In some situations, simply having a reset on a register, regardless of whether it is a high-fanout reset signal, is enough to degrade the performance of your Intel® Stratix® 10 design.
For more in-depth explanation, refer to the Synchronous Resets and Limitations section in the Intel® Stratix® 10 High-Performance Design Handbook.
Intel® recommends the following design guidelines for resets:
- To improve Intel® Stratix® 10 design performance, do not reset registers that do not hold internal states to reduce reset fanout.
- The reset signal is guaranteed to remain asserted for at least 50 clock cycles. Use this guaranteed assertion by "flushing" chains of registers that have internal states, which further reduces the reset fanout.
- You have the option to pipeline the reset signal inside the RTL module for fanout management, to a depth of no more than 15 pipeline registers for stall-free RTL modules, or no more than 25 pipeline registers for stallable RTL modules. If the RTL module is sufficiently large, pipelining the reset signal might improve design performance.