Programming Support for Jam STAPL Language

The Jam device programming and test language is compatible with PLDs that offer ISP. Programming support for Jam STAPL is offered by an ever-growing number of vendors.

Embedded Programming with Jam STAPL

Jam Standard Test and Programming Language (STAPL) meets the necessary system requirements of in-system programming via an embedded processor, as it offers small file sizes, ease of use, and platform independence. Using Jam STAPL for in-system programming via an embedded processor permits convenient in-field upgrades, easy design prototyping, and fast production. These benefits lengthen the life and enhance the quality and flexibility of end-products. It can also reduce device inventories by eliminating the need to stock and track programmed devices.

How It Works

Using Jam STAPL for in-system programming via an embedded processor takes place in two stages (as shown in Figure 1). First, the Quartus® II development tool generates the Jam STAPL source code, or Jam File (.jam), then stores it in the system memory. The Jam File contains all information required to program the in-system programmability (ISP)-capable device(s), including the programming algorithm and data needed to upgrade one or more devices.

In-system programming using the jam file & jam player via an embedded processor

Figure 1. In-system programming using the Jam File & Jam Player via an embedded processor.

About the Jam File (.jam)

To program Intel FPGA devices using Jam STAPL, designers must first create a Jam File with the Quartus II development software. It is not necessary to recompile existing designs, because the Quartus II software can create a Jam File from a Programmer Object File (.pof). To store a Jam File in erasable programmable read-only memory (EPROM) or Flash memory, it must be converted first to a Hexadecimal (Intel-format) File (.hex) or a similar programming file. Embedded processor software packages or other utilities can automatically convert a Jam File for EPROM or Flash programming. Similarly, some EPROM programmers support "raw binary" or "absolute binary" formats, which allow the Jam File to be read directly by the programmer without conversion.

Figure 2 describes how to generate a Jam File for in-system programming.

Generating a jam file

Figure 2. Generating a Jam File.

About the Jam Player

The Jam Player is a C program that parses the Jam File, interprets each Jam STAPL instruction, and reads and writes data to and from the JTAG chain. The variables processed by the Jam Player depend on the initialization list variables present at the time of execution. Because each application has unique requirements, the Jam Player source code can be modified easily.

Figure 3 illustrates the Jam Player source code structure.

Jam player source code structure

Figure 3. Jam Player source code structure.

Note:

  1. TCK, TMS, TDI, and TDO are the JTAG I/O pins.

The main program performs all of the basic functions of the Jam Player without modification. Only the I/O functions must be modified. They are contained in the jamstub.c file, as shown in Figure 3, and include functions which specify addresses to I/O pins, delay routines, operating system-specific functions, and routines for file I/O pins. These functions can be customized by simply editing the jamstub.c file to then compile the source code for use on any platform.

The Jam Player resides permanently in system memory, where it interprets the commands given in the Jam File and generates a binary data stream for device programming. This structure confines all upgrades to the Jam File, and it allows the Jam Player to adapt to any system architecture.

Frequently Asked Questions

ISP & the Jam STAPL

The Jam Standard Test and Programming Language (STAPL) was created by Intel® FPGA engineers and is supported by a consortium of programmable logic device (PLD) manufacturers, programming equipment makers, and test equipment manufacturers. Jam STAPL was adopted as JEDEC standard JESD-71 in August, 1999.

Jam STAPL addresses the issues that designers face when programming PLDs in-system. These issues include proprietary file formats, vendor-specific programming algorithms, large file sizes, and long programming times. Jam STAPL is a major step forward in providing a software-level standard for in-system programming (ISP).

How Jam STAPL Works

The Jam STAPL programming solution consists of two components: the Jam Composer and the Jam Player.

The Jam Composer is a software program, generally written by a programmable logic vendor that writes a Jam File (.jam) that contains the user data and programming algorithm required to program a design into a device.

The Jam Player is software that reads the Jam File and applies vectors for programming and testing devices in a JTAG chain. Embedded system developers can also use a Jam Player to program devices in their system. Most of the source code required for the Jam Player is contained in the Jam STAPL Developer's Kit available from the Jam STAPL web site. The only software routines required to complete the Jam Player are those needed to access the JTAG chain. Figure 1 shows a basic Jam STAPL flow.

Documentation

Frequently Asked Questions

Jam Programming Support: JTAG Technologies

JTAG Technologies* provides a full range of in-system programming and PCB testing solutions based on the boundary-scan IEEE Standard 1149.1 and related standards, including IEEE 1532. These solutions cover all development phases, including design support, prototype debug, production, and repair.

PLD Programming Development

JTAG Technologies* products support programmable logic device (PLD) programming, including the JAM standard programming and test language (STAPL) and Serial Vector File (.svf) formats. As a result, programming capability is available for Intel® FPGA MAX® II, MAX 7000 and MAX 3000A. Regardless of the device type, brand, or format used, the system presents a common interface to the user, avoiding the proliferation of tools. Rapidly created files perform all device operations on-board, such as erase, blank-check, programming, verification, security fuse programming, and user-code readback.

The JTAG ProVision* development system handles a wide variety of scan-chain configurations, ranging from the simple single-chain structure up to multi-chain, multi-level hierarchical scan architectures. Scan chains of any length are possible, with automatic safe configuring of the board during PLD programming. The software GUI guides you in verifying boundary-scan description language (BSDL) files, testing the board's boundary-scan chain, and performing the programming functions.

Production Support

JTAG Technologies' PLD programming applications run on a wide variety of fully-compatible hardware controllers in a broad range of operating environments. Interfaces are available for PCI*, PXI, USB, Ethernet, FireWire, ISA, and VXI. The production environment includes:

  • Stand-alone PC or workstation versions, with an easy-to-use graphical interface for sequencing operations
  • Full integration within an existing production step, such as functional test, by means of dynamic linked library-based (DLL-based) applications
  • Support for incorporating PLD programming within the National Instruments LabWindows/CVI, LabVIEW platform or NI TestStand

JTAG Technologies' tools allow PLD programming to be sequenced with other powerful boundary-scan applications, such as board testing and in-system flash programming. Multiple authorization levels are provided for operators, technicians, and engineers. Production personnel benefit from having quick and easy controls, typically via single-button operation, and execution reports that summarize the results.

Jam STAPL Language Vendor Support

The Jam Standard Test and Programming Language (STAPL) is compatible with programmable logic devices (PLDs) that offer in-system programmability (ISP). Jam STAPL is a major step forward in providing a software-level standard for in-system programming. Programming support for Jam STAPL is offered by an ever-growing number of vendors.

Vender Description
ASSET InterTech, Inc.
  • The company's product family, collectively known as ScanWorks*, provides a set of powerful tools to access, manage, and manipulate boundary-scan paths, allowing ScanWorks tools to be used to program devices in simple or complex scan paths. ASSET tools have long been used to perform in-system programming of programmable devices such as programmable logic devices (PLDs), FPGAs, and Flash memories. ASSET's tools support in-system programmability (ISP) throughout a product's life cycle, from the design/debug process, through the manufacturing/assembly process, to system repair and reprogramming in the field.
  • ScanWorks* ISP features are implemented as ScanWorks Actions, just the same as JTAG test features, enabling test and programming to be done on the same test platforms and from the same application programs. ScanWorks ISP is supported with all ScanWorks hardware options
Corelis, Inc.
  • The Corelis* ScanExpress enables concurrent (gang) testing and in-system programming of CPLDs and flash devices for multiple boards using a single PC and a single operator. ScanExpress addresses very high-speed boundary-scan applications and high-volume production. The ScanExpress family of products dramatically increases test and in-system programming throughput by applying innovative and proprietary techniques.
GÖPEL Electronic
  • Goepel Electronics provides software and hardware products for advanced IEEE Standard 1149.x (JTAG) boundary-scan solutions. Products include the award winning SCANFLEX hardware platform and the integrated development environment SYSTEM CASCON for standard and extended JTAG/boundary-scan test (BST) and in-system applications.
JTAG Technologies
System General
  • The Jam Standard Test and Programming Language (STAPL) player is supported on SG manual and automated programming systems. Major SG models include the T9600 manual programmer and AP520, AP600 automated programming systems.
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