Design Entry and Planning Resource Center
The design entry and planning support center provides resources to plan the FPGA design structure, as well as HDL coding styles that can improve the the quality of the design.
Introduction
FPGA provides guidelines on planning and structuring your design, as well as details about managing metastability in your design, and HDL coding styles that can have a significant effect on the quality of your design's results.
You can also refer to the Quartus® Prime Design Software for a quick overview of design entry and planning.
Table 1. Documentation
| Standard Edition | Description |
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|---|---|---|
| The Quartus® Prime software includes the Platform Designer system integration tool. Platform Designer simplifies the task of defining and integrating custom IP components (IP cores) into your FPGA design. | ||
Platform Designer interconnect is a high-bandwidth structure that allows you to connect IP components to other IP components with various interfaces. |
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You can use the Quartus® Prime software to analyze the average mean time between failures (MTBF) due to metastability caused by synchronization of asynchronous signals, and optimize the design to improve the metastability MTBF. |
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This chapter provides Hardware Description Language (HDL) coding style recommendations to ensure optimal synthesis results when targeting FPGA devices. |
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This user guide describes low-level HDL design techniques using small architectural building blocks and assignments to specify a particular hardware implementation. |
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| This section describes basic design techniques that ensure optimal synthesis results for designs that target FPGA devices while avoiding common causes of unreliability and instability. | ||
In FPGA designs, synchronization of asynchronous signals can cause metastability. You can use the Quartus® Prime software to analyze the mean time between failures (MTBF) due to metastability. A high metastability MTBF indicates a more robust design. |
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This user guide discusses hand-crafted techniques you can use to optimize design blocks for the Adaptive Logic Modules (ALMs). The document includes a collection of circuit building blocks and related discussions, and each section includes a list of example design files you can use for testing and to better understand the derivation of the more complex optimizations. |
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Table 2. Training and Demonstrations
Title |
Description |
|---|---|
| External Memory Interfaces in Agilex™ FPGAs (Part 4): On-Chip Debugging (Log in required to access learn.altera.com) | This training is part 4 of 4. Altera® Agilex™ FPGAs introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR5 running at up to 5.6 Gbps on some devices. 66 Minute Course |
Using the Altera® Quartus® Prime Standard Edition Software: An Introduction (Online course) |
In this introductory training, you will become familiar with the basics of the easy-to-use Altera® Quartus® Prime Standard Edition software design environment. You will learn about the steps involved in the basic FPGA design flow and how to use the software in the flow, going from design entry to device programming all within one tool. 80 Minute Course |
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(Online course) (Instructor-Led course) |
This course will provide an overview of the Verilog hardware description language (HDL) and its use in programmable logic design.
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(Instructor-Led course) |
This instructor-led class is taught in a virtual classroom over 2 half days of instruction. To perform the lab exercises, you will connect to a remote computer provided by Altera® FPGA Training and pre-configured with all the necessary tools. Information required to connect to the remote system will be provided during the class. 2 half days of instruction |