Design Entry and Planning Resource Center
Intel® FPGA provides guidelines on planning and structuring your design, as well as details about managing metastability in your design, and HDL coding styles that can have a significant effect on the quality of your design's results. For information on design entry, planning, and guidelines, refer to:
You can also refer to the Quartus® II software design entry page for a quick overview of design entry features.
To search for known design-related issues and technical support solutions, use Intel FPGA’s knowledge database. You can also visit the Intel FPGA forum to connect with other Intel FPGA users and discuss technical issues. For further technical support, use mySupport to create, view, and update service requests.
Design Entry and Planning Resources
Table 1 provides links to documentation on design entry and planning, including design guidelines.
Table 1. Design Entry and Planning Documentation
Title |
Description |
|---|---|
This chapter of the Quartus II Handbook discusses important FPGA design planning issues, provides recommendations, and describes various tools available for Intel FPGAs to help you improve design productivity. |
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This chapter of the Quartus II Handbook describes synchronous design practices and recommended design techniques. It also describes the Quartus II design assistant that helps find potential design problems. |
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This chapter of the Quartus II Handbook describes the Quartus II analysis, reporting, and optimization features that can help you manage metastability in Intel FPGA devices. It also provides design guidelines that will reduce metastability effects. |
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This chapter of the Quartus II Handbook provides Verilog HDL and VHDL coding style recommendations and examples, including inference of Intel FPGA megafunctions and device-specific coding guidelines. |
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This user guide describes low-level HDL design techniques using small architectural building blocks and assignments to specify a particular hardware implementation. |
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Advanced synthesis cookbook: A design guide for Stratix® II, Stratix® III and Stratix® IV devices |
This user guide discusses hand-crafted techniques you can use to optimize design blocks for the adaptive logic modules (ALMs) in Stratix II, Stratix III, and Stratix IV FPGAs. The document includes a collection of circuit building blocks and related discussions, and each section includes a list of example design files you can use for testing and to better understand the derivation of the more complex optimizations. |
This chapter of the Quartus II Handbook documents the design flow and language support in Quartus II software. It explains how to improve and control your synthesis results with Quartus II synthesis options, attributes, and other features. It also discusses node-naming conventions and how to preserve nodes through synthesis. |
Table 2 provides links to training and demonstrations on design entry and planning, including design guidelines.
Table 2. Design Entry and Planning Training and Demonstrations
Title |
Description |
|---|---|
Design entry |
You will see how to set up a project and enter a design in Quartus II software. |
Design planning guidelines for high-density FPGAs |
You will learn how to avoid pin layout, power consumption, and timing issues with proper design planning techniques. |
VHDL basics |
You will get an overview of the VHDL language and its use in programmable logic design. |
Introduction to VHDL |
You will get a general introduction to the VHDL language and its use in programmable logic design. The emphasis is on the synthesis constructs of VHDL; however, you will also learn about the simulation constructs. You will gain a basic understanding of VHDL to enable you to begin creating your design. You will gain hands-on experience by implementing various simple but practical designs. |
Advanced VHDL design techniques |
You will learn efficient coding techniques for VHDL synthesis, particularly for Intel FPGA devices. You will gain experience writing behavioral and structural code and learn how to effectively code common logic functions including registered, memory, and arithmetic functions. This is a 1-day instructor-led course. |
Verilog HDL basics |
You will get an overview of the Verilog HDL language and its use in programmable logic design. This is a 1-hour online course. |
Introduction to Verilog HDL |
You will learn how to implement basic constructs and modeling structures in Verilog to create an optimal FPGA design. The emphasis is on the synthesis constructs of Verilog HDL; however, you will also learn about the simulation constructs. You will also learn how to take advantage of various features in Verilog HDL such as delays in programmable logic design. You will gain hands-on experience by implementing various simple but practical designs. This is a 1-day instructor-led course. |
Advanced Verilog HDL design techniques |
You will learn efficient coding techniques for writing synthesizable Verilog, particularly for Intel FPGA devices. You will gain experience in writing behavioral and structural code and implementing state machines with multiple efficient coding styles. You will also learn how to optimize a design to an FPGA. This is a 1-day instructor-led course. |
Using the Quartus II software: Schematic design Chinese version: Using the Quartus II software: Schematic design |
You will learn how to use the Quartus II software graphic editor to create a schematic design. You will learn how to utilize the library of functions installed with Quartus II software (e.g., multipliers, filters, etc.). You will also learn how to generate your own custom functions.
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