2. Hardware Handoff
All Intel SoC FPGA projects start with a hardware project where various system settings that impact the HPS are entered by the user. These include:
- Pin multiplexing
- Pin settings
- SDRAM settings
- Clock settings
It is the bootloader's job to apply these settings and the process of the bootloader receiving these settings is called the hardware-to-software handoff.
Depending on the exact bootloader and SoC device family, the handoff can take various forms. Typically:
- For Cyclone V and Arria V SoCs, the handoff is a combination of XML files, binary files, and source code files, which are converted to source code and then compiled into the bootloader
- For Intel Arria 10 SoCs, the handoff is contained in a single XML file that is converted to a device tree file and used by the bootloader
- For Intel Stratix 10 SoCs, Intel Agilex 7 SoCs, and Intel Agilex 5 SoCs the handoff information is part of the FPGA configuration bitstream
The primary method of entering or changing the handoff information is through editing them in the Quartus Platform Designer.
In addition to the handoff information, the bootloaders also have various settings that can be selected by the user through the following methods:
- Editing the bootloader source code
- Editing the bootloader device tree when a device tree is used