TFT LCD Controller Reference Design

Recommended for:

  • Device: Cyclone® I/II/II

  • Quartus®: Unknown




Digital Blocks TFT LCD Controller reference design enables you to accelerate the design-in of TFT LCD panel displays in your system. The reference design centers on the Digital Blocks DB9000AVLN TFT LCD Controller intellectual property (IP) core, which is available in netlist or VHDL/Verilog HDL register transfer level (RTL) formats.

The DB9000AVLN core contains an Avalon® Memory-Mapped system interconnect for interfacing to the Nios® II embedded processor and SDRAM or SRAM controllers (either memory can serve as the frame buffer). Software supplied with this reference design runs on the Nios II embedded processor to place an image in the frame buffer memory and invokes the DB9000AVLN core to drive the LCD panel.

Using the Intel® Quartus® Design Software, you can instantiate the TFT LCD Controller reference design in a Cyclone®, Cyclone® II, or Cyclone® III FPGA development kit. See the Demonstrated Intel® Technology section for a complete list of supported Intel® FPGA development kits.

You can connect your LCD panel to the Intel FPGA development kit with the fabrication of an appropriate cable. Please contact Digital Blocks for more details.

Figure 1 shows the TFT LCD Controller reference design block diagram.

Hardware Design Features

  • Wide range of programmable LCD panel resolutions
    • Maximum programmable resolutions of 4096 x 2048
    • Horizontal pixel resolutions from 16 to 4096 pixels in 16-pixel increments
  • Support for 1-port TFT LCD panel interfaces
    • 18-bit digital (6 bits/color) and 24-bit digital (8 bits/color)
  • Support for 2-port LVDS TFT LCD panel interfaces
  • Programmable frame buffer bits-per-pixel (bpp) color depths:
    • 1, 2, 4, 8 bpp mapped through the color palette to 18-bit LCD pixel
    • 16, 18 bpp directly drives 18-bit LCD pixel
    • 24 bpp directly drives 24-bit LCD pixel
  • Color palette RAM to reduce frame buffer memory storage requirements and Avalon system interconnect width
    • 256 entry by 16-bit RAM, implemented as 128 entry by 32 bits
    • Loaded via the slave bus interface statically by the microprocessor or the master bus interface dynamically with each frame by the direct memory access (DMA) controller
  • Programmable output format support
    • RGB 6:6:6 or 5:6:5 on 18-bit digital interface
    • RGB 8:8:8 on 24-bit digital interface
  • Programmable horizontal and vertical timing parameters
    • Front porch, back porch, sync width, pixels-per-line
    • Sync polarity
  • Programmable pixel clock
    • Pixel clock divider from 1 to 128 of bus clock
    • Pixel clock polarity
    • Separate, independent pixel clock input
  • Programmable data enable timing signal
    • Derived from horizontal and vertical timing parameters
    • Display enable polarity
  • Three types of memory
    • 16-word x 32-bit input FIFO, decoupling Avalon system interconnect and LCD panel clock rates. Integrated with DMA controller
    • 255-word x 16-bit color palette RAM
    • 16-word output FIFO
    • FIFO buffers parameterizable in depth and width
  • Power-up and down sequencing support
  • 9 sources of internal interrupts with masking control
  • Little-endian, big-endian, or Windows CE mode
  • Compliance with Avalon Memory-Mapped interface
  • Optional PCI* Interface
  • Fully-synchronous, synthesizable Verilog HDL or VHDL RTL source with rising edge clocking, no gated clocks, and no internal tri-states
  • Modify or integrate the DB9000AVLN core according to your requirements with Digital Blocks hardware and software engineering services

Contact Information

Digital Blocks, Inc.
587 Rock Road
Glen Rock, NJ 07452 USA
Phone: +1 201 251 1281
Fax: +1 201 632 4809