The ADI parallel port SDRAM controller reference design connects SDRAM to the parallel port of an Analog Devices Incorporated (ADI) ADSP-2126x SHARC® digital signal processor and is implemented in Intel® FPGAs and CPLDs. Intel® FPGA supplies the reference design as Verilog HDL source code. The reference design includes a testbench that allows you to test the Verilog HDL source code. The purpose of this reference design is to demonstrate that Intel devices provide a low cost SDRAM interface for ADI SHARC® digital signal processors.
- Runs on the ADDS-21261 Cyclone® FPGA evaluation kit
- Requires 250 to 300 logic elements, no RAM, and 49 pins
- SDRAM controller supports the 8-bit mode of the ADSP-2126x parallel port
- Digital signal processing (DSP) core clock CCLK has a maximum frequency of 200 MHz
- Memory controller supports operation at 66 Mbps
Intel, Analog Devices Inc., and Danville Signal have created a hardware evaluation kit called the ADDS-21261 Cyclone that provides designers with the ability to evaluate a DSP+FPGA combination for a broad range of applications such as professional audio equipment, radar and navigation systems, software-based radios, industrial test and measurement equipment, medical instrumentation, video conferencing, voice recognition, and noise cancellation.
The ADDS-21261 Cyclone uses an Analog Devices ADSP-21261 SHARC® Processor in combination with an EP1C3. Also included in the evaluation kit is Quartus® II Web Edition Design Software, an evaluation version of Analog Devices’ VisualDSP++, and design examples.