This design example demonstrates how to perform external phased-lock loop (PLL) sharing between the SPI-4.2 transmitter and receiver cores.
In normal cases, internal PLL sharing for the SPI-4.2 transmitter and receiver is automatically done by the Quartus® II Synthesis tool during compilation. However, there are special cases in which internal PLL sharing fails to work. For example, the SPI-4.2 ALTLVDS Megafunction of the Stratix® IV GX ES device does not support internal PLL sharing due to a DPA misalignment issue. In this case, a work-around is to use external PLL sharing in order to enable PLL merging.
For more information on how to do internal PLL sharing, refer to Appendix B of the POS-PHY Level 4 MegaCore function user guide (PDF).
For more information on the DPA Misalignment issue in Stratix IV GX ES devices, refer to the Stratix IV GX ES errata sheet.
This design example is created and validated using Quartus II 9.1.
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The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement
Figure 1 shows the block diagram of the functional simulation architecture
The device under test (DUT) module consists of the SPI-4.2 transmitter and receiver cores, the merge_pll unit, the 128-bit host source unit, and the 128-bit agent sink unit. The host source uses the Atlantic™ interface to transmit data to the SPI-4.2 transmitter core, while the 128-bit agent sink receives data from the SPI-4.2 receiver core. The merge_pll unit generates the fast clock, slow clock, and clock enable signals for both the SPI-4.2 transmitter and receiver cores. This unit also generates the rxsys_clk signal for the SPI-4.2 receiver core.
The test bench modules consist of an identical 128-bit host source for the SPI-4.2 transmitter core and a 64-bit variation agent sink module for the SPI-4.2 receiver core. The SPI-4.2 receiver core in the test bench module uses the 64-bit variation data path width. Both the SPI-4.2 transmitter and receiver cores for the test bench modules do not use external PLL sharing. In actual hardware implementation, they can be replaced with any third party SPI-4.2 devices that execute the same functionality.
Figure 2 shows the compilation report of the design example. From the report, the number of PLLs used is 1 out of 8.
Figure 3 shows the clock summary report.
For more information related to SPI-4.2 core protocol and specification, go to:
For detailed explanation on how to perform external PLL sharing between the SPI-4.2 transmitter and receiver cores, go to Intel Knowledge Database: