Nios® II Processor with Tightly Coupled Memory



This design example shows the use of tightly coupled memory in designs that include Nios II processor. By enabling the processor’s tightly-coupled memory host, Nios II processor gains guaranteed fixed low-latency access to on-chip memory for performance critical applications. This design is provided for the following Intel® FPGA development kits:

  • Nios II Embedded Evaluation Kit, Cyclone® III Edition
  • Embedded Systems Development Kit, Cyclone III Edition
  • Stratix® IV GX FPGA Development Kit

Using This Design Example

The use of this design is governed by and subject to the terms and conditions of the Intel® Design Example License Agreement.

Hardware Requirements

  • Nios II core with tightly coupled host
  • On-chip memory
  • DDRx SDRAM controller
  • System timer
  • High-resolution timer
  • Performance counter
  • LED parallel I/Os (PIOs)
  • System identification (ID) peripheral

Figure 1. Nios II system with tightly coupled instruction and data memory.

Related Links

For more information about using this example in your project, go to:

Nios II Software developer’s handbook ›