This design example shows the use of tightly coupled memory in designs that include Nios II processor. By enabling the processor’s tightly-coupled memory host, Nios II processor gains guaranteed fixed low-latency access to on-chip memory for performance critical applications. This design is provided for the following Intel® FPGA development kits:
- Nios II Embedded Evaluation Kit, Cyclone® III Edition
- Embedded Systems Development Kit, Cyclone III Edition
- Stratix® IV GX FPGA Development Kit
Using This Design Example
- Using tightly coupled memory with the Nios II Processor tutorial describes the detailed instructions to create a Nios II system that uses tightly coupled memory.
- tcm.zip contains the C files required to run the design as explained in the document.
- Nios II Ethernet Standard Design Example provides the hardware platform on which the design runs.
The use of this design is governed by and subject to the terms and conditions of the Intel® Design Example License Agreement.
- Nios II core with tightly coupled host
- On-chip memory
- DDRx SDRAM controller
- JTAG UART
- System timer
- High-resolution timer
- Performance counter
- LED parallel I/Os (PIOs)
- System identification (ID) peripheral