Nios® II Ethernet Standard Design Example

The Nios® II Ethernet Standard hardware design example provides a mix of peripherals and memories similar to a typical Nios II processor system. This design interfaces with each hardware component on the Intel® FPGA development kits, such as SDRAM, LEDs, push buttons, and an Ethernet physical interface or media access control (PHY/MAC). You can use the Nios II Ethernet Standard design as a starting point for your own embedded system by adding or removing components to meet your custom requirements.

This design is provided for the following 10 series Intel FPGA development kits:

  • Intel® MAX® 10 NEEK
  • Intel MAX 10 FPGA Development Kit
  • Intel® Cyclone® 10 LP FPGA Evaluation Kit
  • Intel® Arria® 10 SoC Development Kit

Hardware Design Specifications

  • Nios II processor core with JTAG debug module
  • DDRx SDRAM controller/HyperRam memory controller(1) 
  • Ethernet interface 
  • JTAG UART
  • System timer
  • High-resolution timer(2)
  • Performance counter(3)
  • LED parallel I/Os (PIOs)
  • Push-button PIOs
  • System ID peripheral

Note*

  1. Intel Cyclone 10 device only
  2. Intel MAX 10 device only
  3. Intel MAX 10 device only

Newer designs targeted for the 10 series FPGA device family and their respective development kits information are available in the Intel FPGA Design Store.

The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.

 

Legacy Device

 

V series device family and below used design example based on Qsys hierarchical design which has a top-level system and two subsystems, namely: peripherals subsystem and Ethernet subsystem as shown in Figure 1.

This design is provided for the following Altera development kits:

  • Nios II Embedded Evaluation Kit, Cyclone III Edition
  • Embedded Systems Development Kit, Cyclone III Edition
  • Stratix® IV GX FPGA Development Kit
  • Cyclone V GT FPGA Development Kit

Hardware Design Specifications

  • Nios II processor core with JTAG debug module
  • DDRx SDRAM controller
  • Common Flash Interface (CFI) flash memory interface
  • Ethernet interface
  • JTAG UART
  • System timer
  • High-resolution timer
  • Performance counter
  • LED parallel I/Os (PIOs)
  • Push-button PIOs
  • System ID peripheral
Figure 1. Nios II Ethernet Standard Block Diagram

Download the files used in this example:

Cyclone V GT Ethernet Standard design example and their respective development kits information are available in the Intel FPGA Design Store.

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

 

Related Links

Nios II processor documentation

These design examples may only be used within Intel Corporation devices and remain the property of Intel. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Intel expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Intel.