This design example consists only of the hardware design for use with a compatible operating system that supports memory management unit (MMU). The hardware section consists of the Nios® II/f core with MMU enabled with the reset vector pointing to the flash memory and exception vector that points to the DDR3 memory.
You can use this design as a starting point to build your own MMU-enabled Nios® II processor systems. This design supports the following Intel® FPGA development kits:
Hardware Design Specifications
- Nios® II/f core with JTAG debug module
- DDR3 SDRAM controller
- Common Flash Interface (CFI) flash memory interface
- Triple Speed Ethernet media access control (MAC)
- JTAG UART
- System timer
- High-resolution timer
- Performance counter
- LED parallel I/Os (PIOs)
- Push-button PIOs
- System ID peripheral
- TX/RX SGDMA
- On-chip memory
Using This Design Example
The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.
Download the zip files suitable for your kit below.
- 4SGX230 Nios® II MMU zip file (14.1) ›
- 4SGX230 Nios® II MMU zip file (14.0) ›
- 4SGX230 Nios® II MMU zip file (13.1) ›
Note: Cyclone® III device family is not support in ACDS version 14.0 and above.