Welcome to the Intel® Nios® II Precessor Support page! This page is designed to provide extensive documentation and support for the Nios® II family of embedded processors to help you quickly and easily develop and debug your embedded processor systems.
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| Nios II Processor Reference Guide |
This handbook describes the Nios® II processor from a high-level conceptual description to the low-level details of implementation, inlcuding the Nios® II processor architecture, programming model, and instruction set. This handbook answers the question, "What is the Nios II processor?" and is the primary reference for the Nios II architecture. |
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| Nios II Software Developer's Handbook |
This handbook describes the basic information needed to develop embedded software for the Intel FPGA® Nios II processor. The Nios II processor contains new features added after the Intel® Quartus® Prime 14.0 version. The chapters in this handbook describes the Nios® II software development environment, the Nios® II Embedded Design Suite (EDS) tools that are available to you, and the process for developing software. This handbook answers the question, "How do I write applicaitons for the Nios II processor?" and is the primary reference for Nios II software development. |
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| Embedded Design Handbook |
The Embedded Design Handbook describes how to most effectively use the Nios II Embedded Design Suite (EDS) tools, and recommends design styles and practices for developing, debugging, and optimizing Nios II processor-based embedded systems using Intel provided tools. |
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| Embedded Peripherals IP User Guide |
This user guide describes the IP cores provided by Intel® Quartus® Prime Design Software, including the embedded periperhals that work seamlessly with the Nios II processor. |
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| Nios II Release Notes |
These release notes cover the 16.1 through 18.1 releases for the Nios® II Embedded Design Suite (EDS), Nios® II Processor IP, and Embedded Intellectual Property (IP) cores. |
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Nios II Custom Instruction User Guide
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Custom instructions give the ability to tailor the Nios II processor to meet the needs of a particular application. This user guide gives a detailed overview of hte Nios II custom instruction feature.
The Custom Instruction Design Example shows how to implement the cyclic redundancy check (CRC) algorithm as a Nios® II custom instruction. |
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| Nios II Processor Performance Benchmark |
This datasheet lists the performance and logic element (LE) usage for a typical implementation of a Nios® II soft processor and peripherals. |
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| Nios II Flash Programmer User Guide |
This user guide gives a detailed overview of the Nios II Flash Programmer, which sends file contents over a download cable, such as the Intel® FPGA Download Cable, to a Nios II system running on the FPGA, and instructs the Nios II system to write the data to flash memory. |
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| Intel® FPGA Download Cable II User Guide |
This user guide describes the Intel FPGA download cable II, interfaces a USB port on a host computer to an Intel FPGA mounted on a printed circuit board. |
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| Avalon® Verificaiton IP Suite User Guide |
This user guide describes the Avalon® Verification IP Suite, which provides bus functional models (BFMs) to simulate the behavior and facilitate the verification of IP. |
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| AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor |
This reference design demonstrates the JESD204B IP core operating as part of a system that includes: Intel JESD204B transport layer (assembler and deassembler), test pattern generator and checker, core PLL, SPI master, reset sequencer, various dynamic reconfiguration controllers, and the Nios® II processor as the control unit. The key feature of this reference design is the software-based control flow that utilizes the Nios II processor control unit. |
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| AN 740: Nios II Flash Accelerator Using MAX 10 |
The Nios II flash accelerator was introduced as part of the initiative to improve Nios II/f "fast" core performance in real time applications. This document introduces the accelerator and describes the features, parameters, and performance using a MAX 10 FPGA. |
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AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor
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This reference design provides a simple application that implements basic remote configuration features in Nios II-based systems for MAX 10 FPGA devices. The UART interface included in the MAX 10 FPGA Development Kit is used together with Altera UART IP core to provide the remote configuration functionality. |
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| Nios® II Classic Processor Reference Guide |
This handbook describes the Nios® II Classic processor from a high-level conceptual description to the low-level details of implementation. The chapters in this handbook describe the Nios II processor architecture, the programming model, and the instruction set. |
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| Using IEEE-1588 Precise Time Protocol to Create a NOP_WAIT Instruction for the Nios® II Processor (PDF) | This white paper details how you can incorporate precise time into the instruction set of a Nios II processor. |
| Top 7 Reasons to Replace Your Microcontroller with a Intel MAX 10 FPGA (PDF) | This white paper discusses how to differentiate products, meet time-to-market schedules, and navigate processor obsolescence risk with Intel® MAX 10 FPGAs and the Nios II processor. |
| Motor Control Desings with an Integrated FPGA Design Flow (PDF) | This white paper describes a recommended design flow that leverages Intel's FPGAs' adaptability, variable-precision digital signal processing (DSP), and integrated system-level design tools for motor control designs. Designers of motor-driven equipment can take advantage of the performance, integration, and efficiency benefits of this design flow. |
Intel provides one-click download ZIP files that include all the documentation that are related to the Nios II processor.
For more information on our full training curriculum beyond Nios II, please visit:
| Document | Design Files / Design HTML | |
AN 748: Nios II Gen2 Migration Guide |
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| Nios II Classic Processor Reference Guide |
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| Nios II Classic Software Developer’s Handbook |
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| AN 527: Implementing an LCD Controller |
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| AN 548: Nios II Compact Configuration System for Cyclone III |
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| Creating Multiprocessor Nios II Systems Tutorial |
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| Nios II 3C25 Microprocessor with LCD Controller Data Sheet |
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| Nios II 3C120 Microprocessor with LCD Controller Data Sheet |
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| AN 429: Remote Configuration Over Ethernet with the Nios II Processor |
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| AN 459: Guidelines for Developing a Nios II HAL Device Driver |
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| AN 543: Debugging Nios II Software Using the Lauterbach Debugger |
Design Files (.zip) | |
| AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems |
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| AN 346: Using the Nios II Configuration Controller Reference Designs |
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| AN 350: Upgrading Nios Processor Systems to the Nios II Processor |
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| AN 417: Accelerating Functions with the C2H Compiler: Scatter-Gather DMA with Checksum |
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| AN 446: Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer |
Design Files (.zip) | |
| AN 624: Debugging with System Console Over TCP/IP |
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| AN 595: Vectored Interrupt Controller Usage and Applications |
Design Files (.zip) | |
| AN 531: Reducing Power with Hardware Accelerators |
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| AN 371: Automotive Graphics System Reference Design |
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| A Flexible Solution for Industrial Ethernet (PDF) |
This white paper describes the use of Intel FPGAs to deliver a multistandard Industrial Ethernet capability from a single PCB implementation. |
| The "Energy Aware" Appliance Platform (PDF) |
These solutions allow homeowners to monitor appliance energy use via a home area network, appliance manufacturers to provide improved service to customers, and utility companies to lower energy consumption via the Internet. |
| Implementing a Cost-Effective Human-Machine Interface for Home Appliances (PDF) |
This paper explores these technologies, as well as Altera, Altia, and Echelon’s innovative, total-solution architecture for delivering low-cost, high-performance HMIs on virtually any home appliance or consumer device. |
| Generating Panoramic Views by Stitching Multiple Fisheye Images (PDF) |
This white paper discusses an innovative architecture developed by Altera and Manipal Dot Net to generate panoramic views by stitching multiple fisheye images on an FPGA. This architecture provides a complete view of a vehicle’s surroundings to the driver and makes it easier to control and navigate the vehicle. |
| Using FPGAs to Render Graphics and Drive LCD Interfaces (PDF) |
This paper describes the use of FPGAs to add a LCD and GUI display to any embedded system. |
| A Flexible Architecture for Fisheye Correction in Automotive Rear-View Cameras (PDF) |
This paper discusses an innovative architecture developed by Intel and Manipal Dot Net (MDN) to perform fisheye correction on a FPGA when basic camera parameters are known. |
| Creating Low-Cost Intelligent Display Modules with an FPGA and Embedded Processor (PDF) |
LCDs are fast becoming a standard part of the automotive interior. As demand for LCD technology increases, so do methodologies for controlling and creating the displayed graphical content. Traditionally, character-based LCDs and vacuum florescent (VF) displays have been used for low-cost automotive infotainment applications, but low-cost color thin film transistors (TFTs) quickly are becoming a bright alternative. |
| Implementation of CORDIC-Based QRD-RLS Algorithm on Altera Stratix FPGA with Embedded Nios Soft Processor Technology (PDF) |
This white paper describes the implementation of the QR decomposition-based recursive least squares (RLS) algorithm on Intel's Stratix FPGAs. |
| Increase Bandwidth in Medical & Industrial Applications with FPGA Co-Processors (PDF) |
The purpose of this white paper is to discuss the general issues of moving part, or all, of a DSP application onto a PLD using Intel's DSP Builder and SOPC Builder system software design tools. |
Automated Generation of Hardware Accelerators with Direct Memory Access (PDF) |
Traditionally, the problem of generating stand-alone hardware modules has been addressed by C-to-gates methodologies. A very different approach is to generate coprocessors that off-load and enhance performance of a microprocessor running software written in C. An implementation of this methodology is possible only with a supporting ecosystem of tools, which will be demonstrated in this paper. |
| Optimize System Flexibility by Integrating Custom Microprocessors into FPGAs (PDF) |
This paper documents two examples of first-time Nios II processor users who initially chose Intel's soft-core processors to overcome the inflexibility of COTS microprocessors and microcontrollers. |
| Adding Hardware Accelerators to Reduce Power in Embedded Systems (PDF) |
This white paper discusses how not all functions are equally suited to trading circuits for frequency. Functions that operate in parallel run much faster when hardware is available to execute several steps simultaneously, which translates into greater performance for a given clock speed, but also into lower clock speed for a given performance level. Thus, the addition of hardware to a chip design can lower power demands while maintaining performance. |