Nios® II Processors Support

• The Nios® II Gen2 Processor Reference Guide answers the question "What is the Nios II processor?" and is the primary reference for the Nios II processor architecture
• The Nios II Gen2 Software Developer's Handbook answers the question "How do I write applications for the Nios II processor?" and is the primary reference for Nios II software development
• The Embedded Design Handbook describes how to most effectively use the Nios II Embedded Design Suite (EDS) tools and helps to increase the efficiency of developing, debugging, and optimizing Nios II processor-based embedded systems
• The Embedded Peripherals IP User Guide describes embedded peripherals that work seamlessly with the Nios II processor and are included with the Intel® Quartus® Prime software

Intel provides one-click download ZIP files that include all the documentation that are related to the Nios II processor.

• Version 18.0 (.zip)
  
• Version 17.1 (.zip)
• Version 17.0 (.zip)
  
• Version 16.1 (.zip)
  
• Version 16.0 (.zip)
  
• Version 15.1 (.zip)
  
• Version 15.0 (.zip)
  
• Version 14.1 (.zip)
  
• Version 14.0 (.zip)
  
• Version 13.1 (.zip)
  
• Version 13.0 (.zip)
  
• Version 12.1 (.zip)
  
• Version 12.0 (.zip)
  

Release Notes

• Intel FPGA IP Release Notes (Nios II processor release notes and all embedded intellectual property (IP) release notes are combined into one document)
• Nios II Embedded Design Suite Release Notes

Hardware Development

• AN740: Nios II Flash Accelerator Using MAX® 10
• AN527: Implementing an LCD Controller
• AN548: Nios II Compact Configuration System
  • Compact Configuration Design Example for the Nios II Processor
• Creating Multiprocessor Nios II Systems Tutorial
  • Nios II Multiprocessor Design Example
• Nios II Custom Instruction User Guide
  • Nios II Custom Instruction Design Example
• Nios II 3C25 Microprocessor with LCD Controller Data Sheet
• Nios II 3C120 Microprocessor with LCD Controller Data Sheet

Software Development

• AN741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor
  • MAX10 Remote System Upgrade (RSU) over UART for Nios II Processor Design Example
• AN429: Remote Configuration Over Ethernet with the Nios II Processor
  • AN429 Design Files
• AN459: Guidelines for Developing a Nios II HAL Device Driver
  • HAL Device Drivers Design Example
• AN543: Debugging Nios II Software Using the Lauterbach Debugger
  • AN543 Design Files
• My First Nios II Software Tutorial
• NicheStack Technical Manuals
• NicheStack Technical Reference Manual
• Using the NicheStack TCP/IP Stack - Nios II Edition Tutorial
  • Additional Design Files in Design Store
• Using MicroC/OS-II RTOS with the Nios II Processor Tutorial

Platform Designer (formerly Qsys) Development

• Platform Designer (Next-Generation System Integration Tool)
• Platform Designer Support
• Platform Designer
  • Creating a System with Platform Designer
  • Creating Platform Designer Components
  • Platform Designer Interconnect
  • Optimizing Platform Designer System Performance
  • Component Interface Tcl Reference
  • Platform Designer System Design Components
  • Platform Designer (Standard)
• Platform Designer (Standard)
  • Creating a System with Platform Designer (Standard)
  • Creating Platform Designer (Standard) Components
  • Platform Designer (Standard) Interconnect
  • Optimizing Platform Designer (Standard) System Performance
  • Component Interface Tcl Reference
  • Platform Designer (Standard) System Design Components

Training and Demonstrations

• Nios II Processor Online Demonstrations
• Embedded Hardware Training Curriculum
• Software Development Training Curriculum

Design Guidelines and White Papers

• A Flexible Solution for Industrial Ethernet
• The “Energy Aware” Appliance Platform: A New Approach to Energy Control
• Implementing a Cost-Effective Human-Machine Interface for Home Appliances
• Generating Panoramic Views by Stitching Multiple Fisheye Images
• Using FPGAs to Render Graphics and Drive LCD Interfaces
• A Flexible Architecture for Fisheye Correction in Automotive Rear-View Cameras
• Selecting the Right High-Speed Memory Technology for Your System
• Top 7 Reasons to Replace Your MCU with an Intel MAX 10 FPGA
• Motor Control Designs with an Integrated FPGA Design Flow
• AN531: Reducing Power with Hardware Accelerators
• AN371: Automotive Graphics System Reference Design
• Creating Low-Cost Intelligent Display Modules With an FPGA and Embedded Processor
• Implementation of CORDIC-Based QRD-RLS Algorithm on Altera® Stratix® FPGA with Embedded Nios Soft Processor Technology
• Increase Bandwidth in Medical & Industrial Applications with FPGA Co-Processors
• Optimize System Flexibility by Integrating Custom Microprocessors into FPGAs
• AN729: Implementing JESD204B IP Core System Reference Design with Nios II Processor
• Nios II Gen2 Migration Guide

Download and Licensing

• Download Center
• Installation and Licensing

Legacy Documentation

• Nios II Classic Processor Reference Guide
• Nios II Classic Software Developer's Handbook
• Automated Generation of Hardware Accelerators With Direct Memory Access From ANSI/ISO Standard C Functions
• AN323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems
• AN346: Using the Nios II Configuration Controller Reference Designs
• AN350: Upgrading Nios Processor Systems to the Nios II Processor
• AN417: Accelerating Functions with the C2H Compiler: Scatter-Gather DMA with Checksum
• AN446: Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer
  • AN446 Design Files
• AN624: Debugging with System Console Over TCP/IP
  • Debugging with System Console over TCP/IP (SCTCP) Design Example
• Nios II IDE Help System
• Nios II System Architect Design Tutorial
• SOPC Builder User Guide
• Nios II C2H Compiler User Guide
• Adding Hardware Accelerators to Reduce Power in Embedded Systems
• Accelerating Nios II Systems with the C2H Compiler Tutorial
• AN595: Vectored Interrupt Controller Usage and Applications
  • AN595 Design Files
    

The following documents have now been integrated into the Embedded Design Handbook:

• AN391: Profiling Nios II Systems
• AN351: Simulating Nios II Embedded Processor Designs
• Using Tightly Coupled Memory with the Nios II Processor Tutorial
• AN717: Nios II Gen2 Hardware Development Tutorial
• Generic Nios II Booting Methods User Guide
• AN730: Nios II Processor Booting Methods in MAX 10 FPGA Devices
• AN736: Nios II Processor Booting from Altera Serial Flash (EPCQ)
• AN458: Alternative Nios II Boot Methods
• AN540: Nios II MPU Usage
• AN440: Accelerating Nios II Networking Applications
• Platform Designer System Design Tutorial

• Nios II Processor Design Examples
• Nios II Processor Design Examples on the Design Store
• Nios II Processor FAQ
• Nios II Processor Design Contest Papers
• Nios II Processor Performance Benchmarks
• Nios II Flash Programmer User Guide
• Intel FPGA Download Cable II User Guide
• Avalon® Verification IP Suite User Guide
• Development Kits Documentation
• Nios II with MAX 10 FPGAs
• MAX 10 Nios II Embedded Evaluation Kit (NEEK)