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Nios II Processor Reference Guide
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This handbook describes the Nios® II processor from a high-level conceptual description to the low-level details of implementation, inlcuding the Nios® II processor architecture, programming model, and instruction set.
This handbook answers the question, "What is the Nios II processor?" and is the primary reference for the Nios II architecture.
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Nios II Software Developer's Handbook
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This handbook describes the basic information needed to develop embedded software for the Intel FPGA® Nios II processor. The Nios II processor contains new features added after the Intel® Quartus® Prime 14.0 version. The chapters in this handbook describes the Nios® II software development environment, the Nios® II Embedded Design Suite (EDS) tools that are available to you, and the process for developing software.
This handbook answers the question, "How do I write applicaitons for the Nios II processor?" and is the primary reference for Nios II software development.
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Embedded Design Handbook
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The Embedded Design Handbook describes how to most effectively use the Nios II Embedded Design Suite (EDS) tools, and recommends design styles and practices for developing, debugging, and optimizing Nios II processor-based embedded systems using Intel provided tools.
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Embedded Peripherals IP User Guide
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This user guide describes the IP cores provided by Intel® Quartus® Prime Design Software, including the embedded periperhals that work seamlessly with the Nios II processor.
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Nios II Release Notes
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These release notes cover the 16.1 through 18.1 releases for the Nios® II Embedded Design Suite (EDS), Nios® II Processor IP, and Embedded Intellectual Property (IP) cores.
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Nios II Custom Instruction User Guide
Design Example
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Custom instructions give the ability to tailor the Nios II processor to meet the needs of a particular application. This user guide gives a detailed overview of hte Nios II custom instruction feature.
The Custom Instruction Design Example shows how to implement the cyclic redundancy check (CRC) algorithm as a Nios® II custom instruction.
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Nios II Processor Performance Benchmark
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This datasheet lists the performance and logic element (LE) usage for a typical implementation of a Nios® II soft processor and peripherals.
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Nios II Flash Programmer User Guide
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This user guide gives a detailed overview of the Nios II Flash Programmer, which sends file contents over a download cable, such as the Intel® FPGA Download Cable, to a Nios II system running on the FPGA, and instructs the Nios II system to write the data to flash memory.
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Intel® FPGA Download Cable II User Guide
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This user guide describes the Intel FPGA download cable II, interfaces a USB port on a host computer to an Intel FPGA mounted on a printed circuit board.
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Avalon® Verificaiton IP Suite User Guide
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This user guide describes the Avalon® Verification IP Suite, which provides bus functional models (BFMs) to simulate the behavior and facilitate the verification of IP.
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AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor
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This reference design demonstrates the JESD204B IP core operating as part of a system that includes: Intel JESD204B transport layer (assembler and deassembler), test pattern generator and checker, core PLL, SPI master, reset sequencer, various dynamic reconfiguration controllers, and the Nios® II processor as the control unit.
The key feature of this reference design is the software-based control flow that utilizes the Nios II processor control unit.
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AN 740: Nios II Flash Accelerator Using MAX 10
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The Nios II flash accelerator was introduced as part of the initiative to improve Nios II/f "fast" core performance in real time applications. This document introduces the accelerator and describes the features, parameters, and performance using a MAX 10 FPGA.
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AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor
Design Example
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This reference design provides a simple application that implements basic remote configuration features in Nios II-based systems for MAX 10 FPGA devices. The UART interface included in the MAX 10 FPGA Development Kit is used together with Altera UART IP core to provide the remote configuration functionality.
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Nios® II Classic Processor Reference Guide
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This handbook describes the Nios® II Classic processor from a high-level conceptual description to the low-level details of implementation. The chapters in this handbook describe the Nios II processor architecture, the programming model, and the instruction set.
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