EMIF Calibration Checklist

Number

Question

Yes/No

1.

Is the design able to close time in the Quartus Prime or Quartus II software? DDR timing clean.

 

2.

The board layout is following the board layout guideline on the EMI handbook.

 

3.

The pin placement in the design is following the pin guidelines.

 

4.

The device and interface can support the configuration as stated in spec estimator.

 

5.

The memory parameter in the Quartus Prime or Quartus II software accurately represents the operation configuration and condition.

 

6.

The OCT and ODT settings are correct.

 

7.

For single rank DDR3, set the GUI setting to "Dynamic ODT Off"

 

8.

The correct memory timing parameter for the interface that you are using is input into the Quartus Prime or Quartus II software.

 

9.

Do you have the accurate board skews input into the Quartus Prime or Quartus II software wizard?

 

10.

Does the problem exist in the previous version of Quartus Prime or Quartus II software?

 

11.

Regenerate the IP when upgrading the Quartus Prime or Quartus II software version.

 

12.

Did you try using RTL sequencer if Nios® II sequencer failed for RLDRAM II or QDR II interface?

 

13.

Have you check the voltage supply to make sure all the voltage levels are correct? List of voltage are:

  • VCCIO
  • VCCINT
  • VCCD_PLL
  • VCC
  • VTT
  • VREF

 

14.

Are the Addr/Cmd signal terminations done correctly?

 

15.

Are the Addr/Cmd signal center aligned to the memory clock on the memory side?

 

16.

Do you have a floating DM pins?

 

17.

Are the OCT pin connections and OCT rules followed on your board?.

 

18.

Are the Rup and Rdn or Rzq pin connected properly on both FPGA and interface side on your board?

 

19.

Did you modify any UniPHY default constraints?

 

20.

Does the problem exist on just this PCB or a number of PCBs?

 

21.

Does the design pass at different operating temperature?

 

22.

Are the skew between signals within each DQ group 50ps or less?

 

23.

Check if there are warning message on the Quartus Prime or Quartus II report.

 

24.

Does the design pass when running at a lower operating frequency?

 

25.

Does the design pass while using memory with faster memory part?

 

26.

Run the standalone interface that has problem and power down all the other interfaces. Does it pass?

 

27.

Generate an example design with the same device and memory settings and apply the same pin assignment. Does it pass?