Article ID: 000087141 Content Type: Error Messages Last Reviewed: 03/16/2023

Error: Please specify correct phase shifts

Environment

    Quartus® II Subscription Edition
    Avalon ALTPLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You might see this error when using the PLL Intel® FPGA IP with Stratix® V, Arria® V, and Cyclone® V devices and specifying phase shifts for multiple output clocks. The IP might show this error if one or more phase shift settings are not achievable. However, it may also list Actual Phase Shift settings that are also invalid.

Resolution

To get phase shift settings as close as possible to what you desire for multiple output clock frequencies, use the Physical Output Enable option and manually enter the M and N counter values to achieve a VCO frequency that allows you to achieve your required output frequencies as well as a suitable phase step resolution.

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    Related Products

    This article applies to 14 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA

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