Article ID: 000084354 Content Type: Error Messages Last Reviewed: 03/03/2016

Error: Please specify correct phase shifts

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may encounter this error when instantiating the Altera_PLL megafunction with certain output clock phase shift settings.

    For example, an ALTLVDS interface with a dara rate of 700Mbps and deserialization factor of 7, the compilation report shows the output clocks will have 180, 257 and 334 degree phase shifts. However, if you enter these phase shift settings in the Altera_PLL megafunction, the MegaWizard™ Plug-In Manager will report this error.

     

    Resolution

    Enter the phase shift setting as "ps" to replace the degree setting in the Altera_PLL megafunction.

    This issue is fixed in Quartus® II software version 13.1.

    Related Products

    This article applies to 13 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V FPGAs and SoC FPGAs
    Arria® V GT FPGA
    Cyclone® V FPGAs and SoC FPGAs
    Cyclone® V E FPGA
    Cyclone® V SE SoC FPGA

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