Article ID: 000084354 Content Type: Error Messages Last Reviewed: 03/16/2023

Error: Please specify correct phase shifts

Environment

    Quartus® II Subscription Edition
    Avalon ALTPLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You might encounter this error when instantiating the PLL Intel® FPGA IP with certain output clock phase shift settings.

For example, an ALTLVDS interface with a dara rate of 700 Mbps and deserialization factor of 7, the compilation report shows the output clocks will have 180, 257, and 334 degree phase shifts. However, if you enter these phase shift settings in the PLL Intel® FPGA IP, the parameter editor will report this error.

 

Resolution

Enter the phase shift setting as "ps" to replace the degree setting in the PLL Intel® FPGA IP.

This problem is fixed in Quartus® II software version 13.1.

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This article applies to 13 products

Arria® V GX FPGA
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Cyclone® V FPGAs and SoC FPGAs
Cyclone® V E FPGA
Cyclone® V SE SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA

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