Article ID: 000086948 Content Type: Product Information & Documentation Last Reviewed: 06/10/2022

How can I generate a boot loader if I have no external memory interface connected to my Arria®10 FPGA HPS?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® SoC FPGA Embedded Development Suite (SoC EDS) Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the SoC EDS software version 15.1 and later, BSP-Editor will not allow a boot loader to be generated unless emif.xml exists in the software handoff files directory cretaed by the Quartus® Prime software (hps_isw_handoff).

    The emif.xml file is only created in the software handoff folder if the Arria® 10 SoC HPS component has the External Memory Interface conduit enabled.

     

     

     

    Resolution

    To work around this problem in the SoC EDS software version 15.1 and later follow the steps below:

    1. Compile your design in the Quartus Prime software to generate the hps_isw_handoff folder

    2. In a text editor, create a file named emif.xml with the following content and save it to the hps_isw_handoff folder:

        <?xml version="1.0"?>

        <emif>

        </emif>

    3. Create your BSP in BSP-Editor

    This problem is scheduled to be fixed in a future version of the SoC EDS software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 SX SoC FPGA

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