Article ID: 000086587 Content Type: Troubleshooting Last Reviewed: 02/15/2019

Why are the phase shift settings not being implemented correctly in Stratix II, HardCopy II, or Cyclone II device PLLs for designs compiled in Quartus II software version 5.0 SP1 and earlier?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When using the VCO post-scale divide-by-2 counter (k) available in the Stratix® II and HardCopy® II device fast PLLs and in the Cyclone® II device PLLs, Quartus® II software version 5.0 SP1 and earlier is setting the configuration bits corresponding to certain PLL phase shifts incorrectly. This could cause the PLL to lose lock and the output clock frequency to be incorrect or driven by GND. This problem only affects the lower VCO frequency range i.e. 150-520MHz in Stratix II and HardCopy II device fast PLLs and 300-500MHz in Cyclone II device PLLs.

    If possible, you can work around this problem by using a VCO frequency higher than 500MHz for Cyclone II devices or 520MHz for Stratix II and HardCopy II devices.

    For Quartus II software version 5.0 SP1, you can install patch 1.21.

    This problem is fixed in Quartus II software version 5.1.

    Related Products

    This article applies to 4 products

    Stratix® II FPGAs
    HardCopy™ III ASIC Devices
    Stratix® II GX FPGA
    Cyclone® II FPGA

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