Article ID: 000086345 Content Type: Troubleshooting Last Reviewed: 07/07/2021

Why does the Intel® Stratix® 10 FPGA fail to configure when programing a .jic file?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 21.1, an invalid .jic file will be generated when incompatible frequencies are used for ACTIVE_SERIAL_CLOCK  and DEVICE_INITIALIZATION_CLOCK in your Quartus Settings File (.qsf). The configuration flow will fail using this .jic file.

    Resolution

    To avoid this error, make sure your .qsf file has a compatible set of frequencies for ACTIVE_SERIAL_CLOCK and DEVICE_INITIALIZATION_CLOCK. The valid AS_CLK settings can be found in the Intel® Stratix® 10 Configuration User Guide.

     

    A patch is available to check for valid frequencies for ACTIVE_SERIAL_CLOCK  and DEVICE_INITIALIZATION_CLOCK in the Quartus Settings File (.qsf).

    Download and install Patch 0.06 from the appropriate link below.

    Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.06 for Windows (.exe)

    Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.06 for Linux (.run)

    Download the Readme for Intel® Quartus® Prime Pro Edition 21.1 Patch 0.06  (.txt)

    After installing patch 0.06, in your next compilation with an incompatible set of frequencies you will get an error message during the Assembler stage saying "The active serial clock is not supported in device initialization clock"

     

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.2.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.