Yes, the Stratix® III timing models have been updated in the Quartus® II software version 9.0 SP1 to address the following problems:
Added a clock enable path to the M9K and M144K timing models that was missing in the Quartus II version 9.0 and earlier. Refer to Knowledge Database Solution rd04272009_800 for more information.
Corrected the T4 (DDIO_MUX) timing models to accurately analyze timing on DDIO output paths. Refer to Knowledge Database Solutions rd04212009_627 for more information.
Corrected the write leveling delay chain timing models to eliminate the possibility of hardware functional failures in designs implementing DDR3 interfaces with leveling. Refer to Knowledge Database Solution rd04282009_866 for more information.