Description
Yes, the Stratix® III timing models have been updated in the Quartus® II software version 9.0 SP1 to address the following problems:
Resolution
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Added a clock enable path to the M9K and M144K timing models that were missing in the Quartus II version 9.0 and earlier.
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Corrected the T4 (DDIO_MUX) timing models to accurately analyze timing on DDIO output paths.
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Corrected the write leveling delay chain timing models to eliminate the possibility of hardware functional failures in designs implementing DDR3 interfaces with leveling.