Description
Yes, since the release of the Quartus® II software version 9.0 the timing models for the DDIO output delay chains have been updated for Stratix® III devices. These delay chains were incorrectly modeled in Quartus II software versions 9.0 and earlier. The DDIO output delay chains are identified as "T4 (DDIO_MUX)" in the delay chains summary section of the Quartus II software compilation report, and are not user programmable. The timing models in the Quartus II software version 9.0 SP1 have been updated to resolve this issue. This update eliminates the possibility of hardware functional failures in your designs implementing double data rate outputs.
This issue impacts all Stratix III designs implementing double data rate outputs using the ALTDDIO_OUT, ALTDQ_DQS, and ALTMEMPHY megafunctions. If your design implements any of these megafunctions, follow these steps to reanalyze timing margins with the Quartus II software version 9.0 SP1:
Additionally, if your design implements DDR3 DIMM interfaces or DDR3 component interfaces with leveling (daisy-chain topology for address/command signals) refer to the related solution below for details on timing model changes for the write leveling delay chain.