When compiling a Stratix IV DDR3 UniPHY design in the Quartus® II software, you may get hold time violations between the core clock (afi_clk
which is the CLK[0] output of the PLL) and the leveling clock (memphy_leveling_clk
which is CLK[2] output of the PLL).
The hold time violations are caused by skew between the core clock which is on a dual regional clock resource and the leveling clock which is on a global clock resource.
To work around this issue, assign memphy_leveling_clk
clock signal to a dual regional resource.