Description
You may see hold time violations in Core path in Report DDR timing report of DDR3 SDRAM Controller with UniPHY only in HardCopy® revision. This violation could happen when the
pll_afi_clk (clock output c0 of the PLL) is not placed on a global clock network. Global clocks and regional clocks have larger skew in HardCopy IV device family compared to Stratix® IV device family.
Resolution
To avoid the hold timing violations, place the
pll_afi_clk to a global clock network.