Article ID: 000084214 Content Type: Product Information & Documentation Last Reviewed: 09/12/2012

How to prevent PCIe HIP from entering L2 low power state?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In some scenarios, issues may arise when the PCIe HIP enters L2 low power state.

    Some symptoms may include:
       -LTSSM being stuck in L2 low power state
       -PCIe enumeration issues after entering L2

    Resolution

    There are two methods that a user can use to address issues when the PCI Express HIP enters L2 low power state.


    To prevent the PCI Express HIP from entering L2 low power state.
    - Tie pme_to_cr to 1\'b0.

    Another way to address the issue is to implement user logic that will reset the PCIe core when the LTSSM goes to L2.idle.

    Related Products

    This article applies to 3 products

    Stratix® IV GX FPGA
    Arria® II GX FPGA
    Cyclone® IV GX FPGA

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.