Article ID: 000079077 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does PCIe IP core locks up during Power Management sequence?

Environment

  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When system software generates a Power Management event, the PCIe core may not respond properly to Power Management sequence.  As a result,  it may cause system lockup or blue screen.

    To workaround the problem, user should hardwire test_in[7] to high.

    This issue exists in Quartus® II software v10.0SP1 and earlier versions.

    For v10.1, this problem is fixed for Avalon-ST interface. However, if the core is created from SOPC builder (Avalon-MM), you need to set test_in[7]=1 manually to work-around this issue. This problem will be fixed in future software release.

    Related Products

    This article applies to 4 products

    Cyclone® IV GX FPGA
    Arria® II GX FPGA
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA